EFM32TG210F32 Energy Micro, EFM32TG210F32 Datasheet - Page 234

• Manufacturer Part Number: EFM32TG210F32
• Description: MCU 32BIT 32KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Tiny Geckor

Specifications of EFM32TG210F32

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: UART, I2C, SPI
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 17
• Number Of Timers: 1
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Processor To Be Evaluated: EFM32TG210
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

16.5.5 LEUARTn_STARTFRAME - Start Frame Register (Async Reg)
16.5.6 LEUARTn_SIGFRAME - Signal Frame Register (Async Reg)
31:15
14:3
2:0
31:9
8:0
31:9
8:0
Bit
Offset
0x010
Reset
Access
Name
Bit
Offset
0x014
Reset
Access
Name
Bit
2010-12-21 - d0034_Rev0.90
For more information about Asynchronous Registers please see Section 5.3 (p. 18) .
For more information about Asynchronous Registers please see Section 5.3 (p. 18) .
Reserved
DIV
Specifies the fractional clock divider for the LEUART.
Reserved
Reserved
STARTFRAME
When a frame matching STARTFRAME is detected by the receiver, STARTF interrupt flag is set, and if SFUBRX is set, RXBLOCK
is cleared. The start-frame is be loaded into the RX buffer.
Reserved
SIGFRAME
When a frame matching SIGFRAME is detected by the receiver, SIGF interrupt flag is set.
Name
Name
Name
0x000
0x000
0x000
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
RW
RW
RW
Access
Access
Access
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234
Bit Position
Bit Position
Fractional Clock Divider
Start Frame
Signal Frame
Description
Description
Description
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