EFM32TG210F32 Energy Micro, EFM32TG210F32 Datasheet - Page 217

• Manufacturer Part Number: EFM32TG210F32
• Description: MCU 32BIT 32KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Tiny Geckor

Specifications of EFM32TG210F32

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: UART, I2C, SPI
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 17
• Number Of Timers: 1
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Processor To Be Evaluated: EFM32TG210
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

31:11
10:8
7:5
4
3
2
1
0
Bit
2010-12-21 - d0034_Rev0.90
Reserved
FORMAT
Configure the data-width used internally for I2S data
Reserved
DELAY
Set to add a one-cycle delay between a transition on the word-clock and the start of the I2S word. Should be set for standard I2S format
DMASPLIT
When set DMA requests for right-channel data are put on the TXBLRIGHT and RXDATAVRIGHT DMA requests.
JUSTIFY
Determines whether the I2S data is left or right justified
MONO
Switch between stereo and mono mode. Set for mono
EN
Set the U(S)ART in I2S mode.
Name
Value
0
1
2
3
4
5
6
7
Value
0
1
Mode
W32D32
W32D24M
W32D24
W32D16
W32D8
W16D16
W16D8
W8D8
Mode
LEFT
RIGHT
0x0
0
0
0
0
0
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
RW
RW
RW
RW
RW
RW
Access
Description
32-bit word, 32-bit data
32-bit word, 32-bit data with 8 lsb masked
32-bit word, 24-bit data
32-bit word, 16-bit data
32-bit word, 8-bit data
16-bit word, 16-bit data
16-bit word, 8-bit data
8-bit word, 8-bit data
Description
Data is left-justified
Data is right-justified
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217
I2S Word Format
Delay on I2S data
Separate DMA Request For Left/Right Data
Justification of I2S Data
Stero or Mono
Enable I2S Mode
Description
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