EFM32TG210F32 Energy Micro, EFM32TG210F32 Datasheet - Page 258

• Manufacturer Part Number: EFM32TG210F32
• Description: MCU 32BIT 32KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Tiny Geckor

Specifications of EFM32TG210F32

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: UART, I2C, SPI
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 17
• Number Of Timers: 1
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Processor To Be Evaluated: EFM32TG210
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

17.4 Register Map
17.5 Register Description
17.5.1 TIMERn_CTRL - Control Register
31:30
29
28
Offset
0x000
0x004
0x008
0x00C
0x010
0x014
0x018
0x01C
0x020
0x024
0x028
0x030
0x034
0x038
0x03C
0x040
0x044
0x048
0x04C
0x050
0x054
0x058
0x05C
Offset
0x000
Reset
Access
Name
Bit
2010-12-21 - d0034_Rev0.90
The offset register address is relative to the registers base address.
Reserved
RSSCOIST
When enabled, compare output is set to COIST value at Reload-Start event
ATI
Enable ATI makes CCPOL always track the polarity of the inputs
Name
Name
TIMERn_CTRL
TIMERn_CMD
TIMERn_STATUS
TIMERn_IEN
TIMERn_IF
TIMERn_IFS
TIMERn_IFC
TIMERn_TOP
TIMERn_TOPB
TIMERn_CNT
TIMERn_ROUTE
TIMERn_CC0_CTRL
TIMERn_CC0_CCV
TIMERn_CC0_CCVP
TIMERn_CC0_CCVB
TIMERn_CC1_CTRL
TIMERn_CC1_CCV
TIMERn_CC1_CCVP
TIMERn_CC1_CCVB
TIMERn_CC2_CTRL
TIMERn_CC2_CCV
TIMERn_CC2_CCVP
TIMERn_CC2_CCVB
0
0
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
RW
RW
Access
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258
Bit Position
Type
RW
W1
R
RW
R
W1
W1
RWH
RW
RWH
RW
RW
RWH
R
RWH
RW
RWH
R
RWH
RW
RWH
R
RWH
Reload-Start Sets Compare Ouptut initial State
Always Track Inputs
Description
Description
Control Register
Command Register
Status Register
Interrupt Enable Register
Interrupt Flag Register
Interrupt Flag Set Register
Interrupt Flag Clear Register
Counter Top Value Register
Counter Top Value Buffer Register
Counter Value Register
I/O Routing Register
CC Channel Control Register
CC Channel Value Register
CC Channel Value Peek Register
CC Channel Buffer Register
CC Channel Control Register
CC Channel Value Register
CC Channel Value Peek Register
CC Channel Buffer Register
CC Channel Control Register
CC Channel Value Register
CC Channel Value Peek Register
CC Channel Buffer Register
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