EFM32TG210F32 Energy Micro, EFM32TG210F32 Datasheet
EFM32TG210F32
Specifications of EFM32TG210F32
Related parts for EFM32TG210F32
EFM32TG210F32 Summary of contents
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EFM32TG Reference Manual "Tiny Gecko" Series Preliminary 32-bit high performance at 8-bit ultra low power consumption and cost • 32-bit ARM Cortex-M3 processor running MHz • Flash and 4 KB RAM memory ...
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Energy Friendly Microcontrollers 1.1 EFM32TG Typical Applications The EFM32TG Tiny Gecko is the superior choice for demanding 8-, 16-, and 32-bit low energy applications. Portable and battery operated systems benefit from the 8-bit power consumption and cost combined with ...
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About This Document This document contains reference material for the EFM32TG Tiny Gecko series of Microcontrollers. All modules and peripherals in the Tiny Gecko series devices are described in general terms. Not all modules are present in all devices ...
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Registers and bit fields marked with reserved are reserved for future use. These should be written to 0 unless otherwise stated in the Register Description. Reserved bits might be read future devices. Reset Value The reset value ...
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System Overview 3.1 Introduction The EFM32 MCUs are the world’s most energy friendly microcontrollers. With a unique combination of the powerful 32-bit ARM Cortex-M3, innovative low energy techniques, short wake-up time from energy saving modes, and a wide selection ...
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Asynchronous pulse counting/quadrature decoding • Watchdog Timer with dedicated RC oscillator @ 50 nA • Ultra low power precision analog peripherals • 12-bit 1 Msamples/s Analog to Digital Converter • 8 input channels and on-chip temperature sensor • Single ...
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Figure 3.1. Diagram of EFM32TG Tiny Gecko Core and Memory ARM Cortex-M3 processor Debug Flash RAM Interface Memory Memory Serial Interfaces External USART Interrupts Low Pin Energy Reset UART Note In the block diagram, color indicates availability ...
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Table 3.1. Energy Mode Description Energy Mode Name EM0 – Energy Mode (Run mode) EM1 – Energy Mode (Sleep Mode) EM2 – Energy Mode ...
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Table 3.2. EFM32TG Microcontroller Family 108F4 108F8 108F16 108F32 110F4 110F8 ...
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System Processor Cor bit ALU Hardware divider Control Logic Instruction Interface NVIC Interface 4.1 Introduction The ARM Cortex-M3 (r2p1) 32-bit RISC processor provides outstanding computational performance and exceptional ...
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Unaligned data storage and access • Continuous storage of data requiring different byte lengths • Data access in a single core access cycle • Integrated power modes • Sleep Now mode for immediate transfer to low power state • ...
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Table 4.1. Interrupt Request Lines (IRQ) IRQ # 2010-12-21 - d0034_Rev0.90 ...the world's most energy friendly microcontrollers ...
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Memory and Bus System ARM Cor Con t r olle r 5.1 Introduction The EFM32TG contains 3 main memory segments which can be accessed by the Cortex-M3 ...
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Figure 5.1. System Address Space The embedded SRAM is located at address 0x20000000 in the memory map of the EFM32TG. When running code located in SRAM starting at this address, the Cortex-M3 uses the System bus interface to fetch instructions. ...
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To ...
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Table 5.2. Memory System Low Energy Peripherals Low energy peripherals Address range 0x4008A400 – 0x400BFFFF 0x4008C000 – 0x4008C3FF 0x4008A000 – 0x4008A3FF 0x40088400 – 0x40089FFF 0x40088000 – 0x400883FF 0x40086C00 – 0x40087FFF 0x40086000 – 0x400863FF 0x40084800 – 0x40085FFF 0x40084000 – 0x400843FF 0x40082400 ...
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Table 5.3. Memory System Peripherals Peripherals Address range 0x40010C00 – 0x4007FFFF 0x40010400 – 0x400107FF 0x40010000 – 0x400103FF 0x4000E400 – 0x4000FFFF 0x4000CC00 – 0x4000DFFF 0x4000C400 – 0x4000C7FF 0x4000C000 – 0x4000C3FF 0x4000A400 – 0x4000BFFF 0x4000A000 – 0x4000A3FF 0x40008400 – 0x40009FFF 0x40007000 – ...
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The Bus Matrix accepts new transfers to be initiated by each master in each cycle without inserting any wait-states. However, the slaves may insert wait-states depending on their internal throughput and the clock frequency. The Cortex-M3 and the DMA Controller, ...
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Low Energy Peripheral being accessed. Registers requiring synchronization are marked "Asynchronous in their description header. Note On the Gecko series of devices, all LE peripherals are subject to delayed synchronization. 5.3.1.1.1 Delayed synchronization After writing data to ...
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If compatibility with the Gecko series is a requirement for a given application, the rules that apply to delayed synchronization with respect to SYNCBUSY should also be followed for the peripherals that support immediate synchronization. 5.3.1.2 Reading When reading from ...
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memory • Page size of 512 bytes (minimum erase unit) • Minimum 20K erase cycles endurance • Greater than 10 years data retention at 85°C • Lock-bits for memory protection • Data retention in ...
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DI Address Register 0x0FE081BA ADC0_CAL_5VDIFF 0x0FE081BC ADC0_CAL_2XVDDVSS 0x0FE081BE ADC0_TEMP_0_READ_1V25 0x0FE081C0 RESERVED 0x0FE081C2 RESERVED 0x0FE081C4 RESERVED 0x0FE081C8 DAC0_CAL_1V25 0x0FE081CC DAC0_CAL_2V5 0x0FE081D0 DAC0_CAL_VDD 0x0FE081D4 RESERVED 0x0FE081D8 RESERVED 0x0FE081DC HFRCO_CALIB_BAND_1 0x0FE081DD HFRCO_CALIB_BAND_7 0x0FE081DE HFRCO_CALIB_BAND_11 0x0FE081DF HFRCO_CALIB_BAND_14 0x0FE081E0 HFRCO_CALIB_BAND_21 0x0FE081E1 HFRCO_CALIB_BAND_28 0x0FE081E2 AUXHFRCO_CALIB_BAND_1 0x0FE081E3 ...
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DBG - Debug Interface ARM Cor DBG 6.1 Introduction The EFM32TG devices include hardware debug support through a 2-pin serial-wire debug interface. In addition there is also a 1-wire ...
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When debug access is locked, the debug interface remains accessible, but the connection to the Cortex- M3 core is blocked. This mechanism is controlled by the Authentication Access Port (AAP) as illustrated by Figure 6.1 (p. 24) . Figure 6.1. ...
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Register Map The offset register address is relative to the registers base address. Offset Name 0x000 AAP_CMD 0x004 AAP_CMDKEY 0x008 AAP_STATUS 0x0FC AAP_IDR 6.6 Register Description 6.6.1 AAP_CMD - Command Register Offset 0x000 Reset Access Name Bit Name Reset ...
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Bit Name Reset The key value must be written to this register to write enable the AAP_CMD register. Value Mode 0xCFACC118 WRITEEN 6.6.3 AAP_STATUS - Status Register Offset 0x008 Reset Access Name Bit Name Reset 31:1 Reserved To ensure compatibility ...
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MSC - Memory System Controller 01000101011011100110010101110010 01100111011110010010000001001101 01101001011000110111001001101111 00100000011100100111010101101100 01100101011100110010000001110100 01101000011001010010000001110111 01101111011100100110110001100100 00100000011011110110011000100000 01101100011011110111011100101101 01100101011011100110010101110010 01100111011110010010000001101101 01101001011000110111001001101111 01100011011011110110111001110100 01110010011011110110110001101100 01100101011100100010000001100100 01100101011100110110100101100111 01101110001000010100010101101110 7.1 Introduction The Memory System Controller (MSC) is the program memory unit ...
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Features • AHB read interface • Scalable access performance to optimize the Cortex-M3 code interface • Zero wait-state access MHz and one wait-state for 16 MHz and above • Advanced energy optimization functionality • Conditional branch ...
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Table 7.1. MSC Flash Memory Mapping Block Page Base address 1 Main 0 0x00000000 . 63 0x00007E00 Reserved - 0x00020000 Information 0 0x0FE00000 - 0x0FE00200 1 0x0FE04000 - 0x0FE04200 2 0x0FE08000 - 0x0FE08200 Reserved - 0x0FE10000 1 Block/page erased by ...
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A page is locked when the bit locked page cannot be erased or written. Word 127 is the debug lock word (DLW). The four LSBs of this word are the ...
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Zero Wait-state Access At 16 MHz and below, read operations from flash may be performed without any wait-states. Zero wait- state access greatly improves code execution performance at frequencies from 16 MHz and below. By default, the Cortex-M3 uses ...
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Figure 7.2. Instruction Cache ICODE AHB-Lite Bus IDCODE AHB-Lite Bus CODE IDCODE Mem ory Space MUX By default, the instruction cache is automatically invalidated when the contents of the flash is changed (i.e. written or erased). In many cases, however, ...
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PERIOD, the number of cycles should at least span 1.1 us, and for the 5 us period they should span at least 5.5 us. For the 7MHz and 1MHz bands recommended ...
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Register Map The offset register address is relative to the registers base address. Offset Name 0x000 MSC_CTRL 0x004 MSC_READCTRL 0x008 MSC_WRITECTRL 0x00C MSC_WRITECMD 0x010 MSC_ADDRB 0x018 MSC_WDATA 0x01C MSC_STATUS 0x02C MSC_IF 0x030 MSC_IFS 0x034 MSC_IFC 0x038 MSC_IEN 0x03C MSC_LOCK ...
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MSC_READCTRL - Read Control Register Offset 0x004 Reset Access Name Bit Name Reset 31:6 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 ( ICCDIS 0 Set this bit ...
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Bit Name Reset 1 IRQERASEABORT 0 When this bit is set to 1, any Cortex-M3 interrupt aborts any current page erase operation. Executing that interrupt vector from Flash will cause an exception. 0 WREN 0 When this bit is set, ...
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MSC_ADDRB - Page Erase/Write Address Buffer Offset 0x010 Reset Access Name Bit Name Reset 31:0 ADDRB 0x00000000 This register holds the page address for the erase or write operation page is 512 bytes, bit [8:0] of this ...
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Bit Name Reset 31:7 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 ( PCRUNNING 0 This bit is set while the performance counters are running. When one performance counter ...
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MSC_IFS - Interrupt Flag Set Register Offset 0x030 Reset Access Name Bit Name Reset 31:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 ( CMOF 0 Set the ...
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MSC_IEN - Interrupt Enable Register Offset 0x038 Reset Access Name Bit Name Reset 31:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 ( CMOF 0 Enable the cache ...
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MSC_CMD - Command Register Offset 0x040 Reset Access Name Bit Name Reset 31:3 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 ( STOPPC 0 Use this commant bit ...
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MSC_CACHEMISSES - Cache Misses Performance Counter Offset 0x048 Reset Access Name Bit Name Reset 31:20 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 19:0 CACHEMISSES 0x00000 Use to ...
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DMA - DMA Controller DMA controller 8.1 Introduction The Direct Memory Access (DMA) controller performs memory operations independently of the CPU. This has the benefit of reducing the energy consumption and the workload of ...
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Scatter-gather (using the primary descriptor to configure the alternate descriptor) • Each channel has a programmable transfer length • A DMA channel can be triggered by any of several sources: • Communication modules (USART, LEUART) • Timers (TIMER) • ...
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Functional Description The DMA Controller is highly flexible capable of transferring data between peripherals and memory without involvement from the processor core. This can be used to increase system performance by off-loading the processor from copying large ...
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Table 8.1 (p. 46) lists the arbitration rates. Table 8.1. AHB bus transfer arbitration interval R_power Arbitrate after x DMA transfers b0000 b0001 b0010 b0011 b0100 x = ...
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Channel Priority level Descending order of number setting channel priority 4 High - 5 High - 6 High - 7 High - 0 Default - 1 Default - 2 Default - 3 Default - 4 Default - 5 Default - ...
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Table 8.3. DMA cycle types cycle_ctrl Description b000 Channel control data structure is invalid b001 Basic DMA transfer b010 Auto-request b011 Ping-pong b100 Memory scatter-gather using the primary data structure b101 Memory scatter-gather using the alternate data structure b110 Peripheral ...
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The controller sets dma_done[C] HIGH for one HFCORECLK cycle. This indicates to the host processor that the DMA cycle is complete. 8.4.2.3.4 Ping-pong In ping-pong mode, the controller performs a DMA cycle using one of the data structures and ...
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The controller sets dma_done[C] HIGH for one HFCORECLK cycle and enters the arbitration process. After task A completes, the host processor can configure the primary data structure for task C. This enables the controller to immediately switch to task ...
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D the controller set the cycle_ctrl bits to b000, then the ping-pong DMA transaction completes. Note You can also terminate the ping-pong DMA cycle in Figure 8.3 (p. 49 you configure task E ...
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Figure 8.4. Memory scatter-gather example Initialization: 1. Configure prim ary to enable the copy and D operations: cycle_ctrl = b100 Write the prim ary source data ory, using the structure shown in ...
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The controller generates an auto-request for the channel and then arbitrates. Task C 9. The controller performs task C. After it completes the task, it generates an auto-request for the channel and then arbitrates. Primary, copy D 10. T ...
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Bit Field Value Description 1 [13:4] n_minus_1 N Configures the controller to perform N DMA transfers, where multiple of four [3] next_useburst - When set to 1, the controller sets the chnl_useburst_set [C] bit to 1 after ...
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Primary, copy A 1. After receiving a request, the controller performs four DMA transfers. These transfers write the alternate data structure for task A. Task A 2. The controller performs task A. 3. After the controller completes the task it ...
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Figure 8.6 (p. 56) ...
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Figure 8.7. Detailed memory map for the 8 channels, including the alternate data structure Unused Control Alternate for channel 7 Destination End Pointer Source End Pointer Unused Control Alternate for channel 1 Destination End Pointer Source End Pointer Unused Control ...
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Destination data end pointer The dst_data_end_ptr memory location contains a pointer to the end address of the destination data. Table 8.8 (p. 58) lists the bit assignments for this memory location. Table 8.8. dst_data_end_ptr bit assignments Bit Name Description ...
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Bit Name Description Note You must set dst_size to contain the same value that src_size contains. [27:26] src_inc Set the bits to control the source address increment. The address increment depends on the source data width as follows: Source data ...
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Bit Name Description [13:4] n_minus_1 Prior to the DMA cycle commencing, these bits represent the total number of DMA transfers that the DMA cycle contains. You must set these bits according to the size of DMA cycle that you require. ...
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Bit Name Description When the controller operates in peripheral scatter-gather mode, you must only use this value in the alternate data structure. At the start of a DMA cycle memory. After it performs ...
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Table 8.11. DMA cycle of 12 bytes using a halfword increment Initial values of channel_cfg, prior to the DMA cycle src_size = b00, dst_inc = b01, n_minus_1 = b1011, cycle_ctrl = 1, R_power = b11 End Pointer 0x5E7 0x5E7 0x5E7 ...
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Example 8.1. DMA Transfer 1. Configure the channel select for using USART1 with DMA channel 0 a. Write SOURCESEL=0b001101 and SIGSEL=XX to DMA_CHCTRL0 2. Configure the primary channel descriptor for DMA channel 0 a. Write XX (read address of USART1) ...
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Register Map The offset register address is relative to the registers base address. Offset Name 0x000 DMA_STATUS 0x004 DMA_CONFIG 0x008 DMA_CTRLBASE 0x00C DMA_ALTCTRLBASE 0x010 DMA_WAITSTATUS 0x014 DMA_CHSWREQ 0x018 DMA_CHUSEBURSTS 0x01C DMA_CHUSEBURSTC 0x020 DMA_CHREQMASKS 0x024 DMA_CHREQMASKC 0x028 DMA_CHENS 0x02C DMA_CHENC ...
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Register Description 8.7.1 DMA_STATUS - DMA Status Registers Offset 0x000 Reset Access Name Bit Name Reset 31:21 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 20:16 CHNUM 0x07 ...
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Bit Name Reset Control wether accesses done by the DMA controller are privileged or not. When CHPROT = 1 then HPROT is HIGH and the access is privileged. When CHPROT = 0 then HPROT is LOW and the access is ...
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DMA_WAITSTATUS - Channel Wait on Request Status Register Offset 0x010 Reset Access Name Bit Name Reset 31:0 WAITSTATUS 0x000000FF Status for wait on request for each channel. 8.7.6 DMA_CHSWREQ - Channel Software Request Register Offset 0x014 Reset Access Name ...
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DMA_CHUSEBURSTS - Channel Useburst Set Register Offset 0x018 Reset Access Name Bit Name Reset 31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 ( CH7USEBURSTS 0 See description ...
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Bit Name Reset 31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 ( CH7USEBURSTC 0 Write disable useburst setting for this channel. 6 CH6USEBURSTC 0 Write ...
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Bit Name Reset Write disable peripheral requests for this channel. 0 CH0REQMASKS 0 Write disable peripheral requests for this channel. 8.7.10 DMA_CHREQMASKC - Channel Request Mask Clear Register Offset 0x024 Reset Access Name Bit ...
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Bit Name Reset 31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 ( CH7ENS 0 Write enable this channel. Reading returns the enable status of the ...
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Bit Name Reset Write disable this channel. Note that the controller disables a channel, by setting the appropriate bit, when either it completes the DMA cycle reads a channel_cfg memory location which has cycle_ctrl = ...
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Bit Name Reset 7 CH7ALTC 0 Write select the primary structure for this channel. 6 CH6ALTC 0 Write select the primary structure for this channel. 5 CH5ALTC 0 Write select the ...
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DMA_CHPRIC - Channel Priority Clear Register Offset 0x03C Reset Access Name Bit Name Reset 31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 ( CH7PRIC 0 Write to ...
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DMA_IF - Interrupt Flag Register Offset 0x1000 Reset Access Name Bit Name Reset 31 ERR 0 This flag is set when an error has occurred on the AHB bus. 30:8 Reserved To ensure compatibility with future devices, always write ...
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Bit Name Reset 31 ERR 0 Set set DMA error interrupt flag. 30:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 ( CH7DONE 0 Write to ...
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Bit Name Reset 2 CH2DONE 0 Write clear the corresponding DMA channel complete interrupt flag. 1 CH1DONE 0 Write clear the corresponding DMA channel complete interrupt flag. 0 CH0DONE 0 Write ...
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DMA_CHx_CTRL - Channel Control Register Offset 0x1100 Reset Access Name Bit Name Reset 31:22 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 21:16 SOURCESEL 0x00 Select input source ...
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Bit Name Reset Value 0b0000 0b0001 0b0010 SOURCESEL = 0b010100 (I2C0) 0b0000 0b0001 SOURCESEL = 0b011000 (TIMER0) 0b0000 0b0001 0b0010 0b0011 SOURCESEL = 0b011001 (TIMER1) 0b0000 0b0001 0b0010 0b0011 SOURCESEL = 0b110000 (MSC) 0b0000 SOURCESEL = 0b110001 (AES) 0b0000 0b0001 ...
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RMU - Reset Management Unit RESETn POWERON BROWNOUT LOCKUP SYSRESETREQ WATCHDOG 9.1 Introduction The RMU is responsible for handling the reset functionality of the EFM32TG. 9.2 Features • Reset sources • Power-on Reset (POR) ...
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As seen in Figure 9.1 (p. 81) the Power-on Reset, Brown-out Detectors and RESETn pin all reset the whole system including the Debug Interface. A Watch Dog timeout, a Core Lockup condition or a System reset request from software resets ...
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Table 9.1. RMU Reset Cause Register Interpretation Register Value 0bXXX XXXX XXX1 0bXXX XXXX XX10 0bXXX XXX0 0100 0bXXX XXXX 1X00 0bXXX XXX1 XX00 0bXXX XX10 0000 0b000 01X0 0000 0b000 1000 0XX0 0b001 1000 0XX0 0b010 0000 0000 0b100 ...
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Figure 9.3. RMU Brown-out Detector Operation V VBODthr V DD BROWNOUTn Unknown 9.3.4 RESETn pin Reset Forcing the RESETn pin low generates a reset of the EFM32TG. The RESETn pin includes an on- chip pull-up resistor, and can therefore be ...
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Register Map The offset register address is relative to the registers base address. Offset Name 0x000 RMU_CTRL 0x004 RMU_RSTCAUSE 0x008 RMU_CMD 9.5 Register Description 9.5.1 RMU_CTRL - Control Register Offset 0x000 Reset Access Name Bit Name Reset 31:1 Reserved ...
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Bit Name Reset 7 EM4RST 0 Set if the system has been in EM4. Must be cleared by software. Please see Table 9.1 (p. 82) for details on how to interpret this bit. 6 SYSREQRST 0 Set if a system ...
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EMU - Energy Management Unit 10.1 Introduction The Energy Management Unit (EMU) manages all the low energy modes (EM) in EFM32TG microcontrollers. Each energy mode manages if the CPU and the various peripherals are ...
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Functional Description The Energy Management Unit (EMU) is responsible for managing the wide range of energy modes available in EFM32TG. An overview of the EMU module is shown in Figure 10.1 (p. 87) . Figure 10.1. EMU Overview Peripheral ...
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Figure 10.2. EMU Energy Mode Transitions Act ive m ode Low energy m odes No direct transitions between EM1, EM2 or EM3 are available, as can also be seen from Figure 10.2 (p. 88) . Instead, a wakeup will transition ...
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Table 10.1. EMU Energy Mode Overview Wakeup time to EM0 MCU clock tree High frequency peripheral clock trees Core voltage regulator High frequency oscillator full functionality Low frequency peripheral clock trees Low frequency oscillator Real Time Counter ...
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EM2 • The high frequency oscillator is inactive (LESENSE may use AUXHFRCO) • The high frequency peripheral and MCU clock trees are inactive • The low frequency oscillator and clock trees are active • Low frequency peripheral functionality (RTC, ...
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Leaving a Low Energy Mode In each low energy mode a selection of peripheral units are available, and software can either enable or disable the functionality. Enabled interrupts that can cause wakeup from a low ...
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Register Map The offset register address is relative to the registers base address. Offset Name 0x000 EMU_CTRL 0x008 EMU_LOCK 0x024 EMU_AUXCTRL 10.5 Register Description 10.5.1 EMU_CTRL - Control Register Offset 0x000 Reset Access Name Bit Name Reset 31:4 Reserved ...
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Bit Name Reset 15:0 LOCKKEY 0x0000 Write any other value than the unlock code to lock all EMU registers from editing. Write the unlock code to unlock. When reading the register, bit 0 is set when the lock is enabled. ...
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CMU - Clock Management Unit WDOG clock LETIMER clock LCD clock Oscillators CMU Peripheral A clock Peripheral B clock Peripheral C clock Peripheral D clock CPU clock 11.1 Introduction The Clock Management Unit (CMU) ...
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Selectable clocks can be output on two pins for use externally. • Auxiliary 1-28 MHz RC oscillator (AUXHFRCO) for flash programming, debug trace, and LESENSE timing. 11.3 Functional Description An overview of the CMU is shown in Figure 11.1 ...
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Figure 11.1. CMU Overview AUXCLK AUXHFRCO Tim eout CMU_HFPERCLKDIV.HFPERCLKEN HFXO Tim eout Tim eout HFRCO CMU_CMD.HFCLKSEL LFXO Tim eout LFRCO Tim eout CMU_LFCLKSEL.LFA / LFAE CMU_LFCLKSEL.LFB / LFBE ULFRCO WDOG_CTRL.CLKSEL 2010-12-21 - d0034_Rev0.90 ...the world's most energy friendly microcontrollers CMU_CTRL_DBGCLK ...
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System Clocks 11.3.1.1 HFCLK - High Frequency Clock HFCLK is the selected High Frequency Clock. This clock is used by the CMU and drives the two prescalers that generate HFCORECLK and HFPERCLK. The HFCLK can be driven by a ...
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LFBCLK - Low Frequency B Clock LFBCLK is the selected clock for the Low Energy B Peripherals. There are four selectable sources for LFBCLK: LFRCO, LFXO, HFCORECLK/2 and ULFRCO. In addition, the LFBCLK can be disabled. From reset, the ...
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Software can switch between the different clock sources at run-time. E.g., when the HFRCO is the clock source, software can switch to HFXO by writing the field HFCLKSEL in the CMU_CMD command register. See Figure 11.2 (p. 99) for a ...
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Figure 11.3. CMU Switching from HFRCO to HFXO after HFXO is ready CMU_CMD.HFCLKSEL CMU_OSCENCMD.HFRCOEN CMU_OSCENCMD.HFRCODIS CMU_OSCENCMD.HFXOEN CMU_OSCENCMD.HFXODIS CMU_STATUS.HFRCORDY CMU_STATUS.HFRCOENS CMU_STATUS.HFRCOSEL CMU_STATUS.HFXORDY CMU_STATUS.HFXOENS CMU_STATUS.HFXOSEL HFCLK HFRCO HFXO Switching clock source for LFACLK and LFBCLK is done by setting the LFA and ...
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Figure 11.5. LFXO Pin Connection It is possible to connect an external clock source to HFXTAL_N/LFXTAL_N pin of the HFXO or LFXO oscillator. By configuring the HFXOMODE/LFXOMODE fields in CMU_CTRL, the HFXO/LFXO can be bypassed. 11.3.3.2 HFRCO, LFRCO and AUXHFRCO ...
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Figure 11.6. HW-support for RC Oscillator Calibration DOWNCLK Dom ain CMU_CALCTRL.DOWNSEL AUXHFRCO HFRCO LFRCO DOWNCLK HFXO LFXO (Default) HFCLK UPCLK Dom ain CMU_CALCTRL.REFSEL AUXHFRCO HFRCO LFRCO HFXO LFXO HFCLK Dom ain The counter operation for single and continuous mode are ...
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Output Clock on a Pin It is possible to configure the CMU to output clocks on two pins. This clock selection is done using CLKOUTSEL0 and CLKOUTSEL1 fields in CMU_CTRL. The output pins must be configured in the CMU_ROUTE ...
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Register Map The offset register address is relative to the registers base address. Offset Name 0x000 CMU_CTRL 0x004 CMU_HFCORECLKDIV 0x008 CMU_HFPERCLKDIV 0x00C CMU_HFRCOCTRL 0x010 CMU_LFRCOCTRL 0x014 CMU_AUXHFRCOCTRL 0x018 CMU_CALCTRL 0x01C CMU_CALCNT 0x020 CMU_OSCENCMD 0x024 CMU_CMD 0x028 CMU_LFCLKSEL 0x02C CMU_STATUS ...
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Register Description 11.5.1 CMU_CTRL - CMU Control Register Offset 0x000 Reset Access Name Bit Name Reset 31:29 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 ( DBGCLK 0 ...
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Bit Name Reset Value Mode 2 16KCYCLES 3 32KCYCLES 17 LFXOBUFCUR 0 This value has been set during calibration and should not be changed. 16:14 Reserved To ensure compatibility with future devices, always write bits to 0. More information in ...
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CMU_HFCORECLKDIV - High Frequency Core Clock Division Register Offset 0x004 Reset Access Name Bit Name Reset 31:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 3:0 HFCORECLKDIV 0x0 ...
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Bit Name Reset Value Mode 0 HFCLK 1 HFCLK2 2 HFCLK4 3 HFCLK8 4 HFCLK16 5 HFCLK32 6 HFCLK64 7 HFCLK128 8 HFCLK256 9 HFCLK512 11.5.4 CMU_HFRCOCTRL - HFRCO Control Register Offset 0x00C Reset Access Name Bit Name Reset 31:17 ...
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CMU_LFRCOCTRL - LFRCO Control Register Offset 0x010 Reset Access Name Bit Name Reset 31:7 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 6:0 TUNING 0x40 Writing this field ...
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CMU_CALCTRL - Calibration Control Register Offset 0x018 Reset Access Name Bit Name Reset 31:7 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 ( CONT 0 Set this bit ...
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Bit Name Reset 19:0 CALCNT 0x00000 Write top value before calibration. Read calibration result from this register when Calibration Ready flag has been set. 11.5.9 CMU_OSCENCMD - Oscillator Enable/Disable Command Register Offset 0x020 Reset Access Name Bit Name Reset 31:10 ...
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CMU_CMD - Command Register Offset 0x024 Reset Access Name Bit Name Reset 31:5 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 ( CALSTOP 0 Stops the calibration counters. ...
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Bit Name Reset Value Mode 0 DISABLED 1 ULFRCO 15:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 3:2 LFB 0x1 Selects the clock source for LFBCLK Value Mode ...
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Bit Name Reset 7 LFRCORDY 0 LFRCO is enabled and start-up time has exceeded. 6 LFRCOENS 0 LFRCO is enabled. 5 AUXHFRCORDY 0 AUXHFRCO is enabled and start-up time has exceeded. 4 AUXHFRCOENS 0 AUXHFRCO is enabled. 3 HFXORDY 0 ...
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CMU_IFS - Interrupt Flag Set Register Offset 0x034 Reset Access Name Bit Name Reset 31:7 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 ( CALOF 0 Write to ...
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Bit Name Reset 4 AUXHFRCORDY 0 Write clear the AUXHFRCO Ready Interrupt Flag 3 LFXORDY 0 Write clear the LFXO Ready Interrupt Flag 2 LFRCORDY 0 Write clear the LFRCO Ready ...
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CMU_HFCORECLKEN0 - High Frequency Core Clock Enable Register 0 Offset 0x040 Reset Access Name Bit Name Reset 31:3 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 ( ...
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Bit Name Reset 5 TIMER1 0 Set to enable the clock for TIMER1. 4 TIMER0 0 Set to enable the clock for TIMER0. 3 USART1 0 Set to enable the clock for USART1. 2 USART0 0 Set to enable the ...
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Bit Name Reset Value Description 0 CMU_LFACLKEN0 is ready for update 1 CMU_LFACLKEN0 is busy synchronizing new value 11.5.20 CMU_FREEZE - Freeze Register Offset 0x054 Reset Access Name Bit Name Reset 31:1 Reserved To ensure compatibility with future devices, always ...
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CMU_LFBCLKEN0 - Low Frequency B Clock Enable Register 0 (Async Reg) Offset 0x060 Reset Access Name Bit Name Reset 31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) ...
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Bit Name Reset Value Mode 9 DIV512 10 DIV1024 11 DIV2048 12 DIV4096 13 DIV8192 14 DIV16384 15 DIV32768 7:4 RTC 0x0 Configure Real-Time Counter prescaler Value Mode 0 DIV1 1 DIV2 2 DIV4 3 DIV8 4 DIV16 5 DIV32 ...
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Bit Name Reset 1:0 LEUART0 0x0 Configure Low Energy UART 0 prescaler Value Mode 0 DIV1 1 DIV2 2 DIV4 3 DIV8 11.5.25 CMU_PCNTCTRL - PCNT Control Register Offset 0x078 Reset Access Name Bit Name Reset 31:2 Reserved To ensure ...
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Bit Name Reset Value Mode 2 DIV4 3 DIV8 4 DIV16 5 DIV32 6 DIV64 7 DIV128 3 VBOOSTEN 0 This bit enables/disables the VBOOST function. 2:0 FDIV 0x0 These bits controls the framerate according to this formula: LFACLK the ...
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Bit Name Reset 31:16 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 15:0 LOCKKEY 0x0000 Write any other value CMU_HFPERCLKDIV, CMU_HFRCOCTRL, CMU_LFRCOCTRL, CMU_AUXHFRCOCTRL, CMU_OSCENCMD, CMU_CMD, CMU_LFCLKSEL, CMU_HFCORECLKEN0, CMU_HFPERCLKEN0, CMU_LFACLKEN0, ...
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WDOG - Watchdog Timer Counter value Watchdog clear Tim eout period 12.1 Introduction The purpose of the watchdog timer is to generate a reset in case of a system failure, to increase application reliability. ...
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Clock Source Three clock sources are available for use with the watchdog, through the CLKSEL field in WDOG_CTRL. The corresponding clocks must be enabled in the CMU. The SWOSCBLOCK bit in WDOG_CTRL can be written to prevent accidental disabling ...
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Register Map The offset register address is relative to the registers base address. Offset Name 0x000 WDOG_CTRL 0x004 WDOG_CMD 0x008 WDOG_SYNCBUSY 12.5 Register Description 12.5.1 WDOG_CTRL - Control Register (Async Reg) For more information about Asynchronous Registers please see ...
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Bit Name Reset 7 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 ( SWOSCBLOCK 0 Set to disallow disabling of the selected WDOG oscillator. Writing this bit to 1 ...
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Bit Name Reset 31:1 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 ( CLEAR 0 Clear watchdog timer. The bit must be written 4 watchdog cycles before the timeout. ...
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PRS - Peripheral Reflex System Tim er ADC DMA 13.1 Introduction The Peripheral Reflex System (PRS) system is a network which lets the different peripheral module communicate directly with each other without involving the ...
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Asynchronous Mode Many reflex signals can operate in two modes, synchronous or asynchronous. A synchronous reflex is clocked on HFPERCLK, and can be used as an input to all reflex consumers, but since they require HFPERCLK, they will not ...
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Table 13.1. Reflex Producers Module Reflex Output ACMP Comparator Output ADC Single Conversion Done Scan Conversion Done DAC Channel 0 Conversion Done Channel 1 Conversion Done GPIO Pin 0 Input Pin 1 Input Pin 2 Input Pin 3 Input Pin ...
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Module Reflex Output IrDA Decoder Output VCMP Comparator Output 13.3.4 Consumers Consumer peripherals (Listed in Table 13.2 (p. 133) ) can be set to listen to a PRS channel and perform an action based on the signal received on that ...
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Set SINGLEPRSEN in ADC0_SINGLECTRL enable single conversions to be started by a high PRS input signal. • Set SINGLEPRSSEL in ADC0_SINGLECTRL to 0x5 to select PRS channel 5 as input to start the single conversion. • ...
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Register Map The offset register address is relative to the registers base address. Offset Name 0x000 PRS_SWPULSE 0x004 PRS_SWLEVEL 0x008 PRS_ROUTE 0x010 PRS_CH0_CTRL 0x014 PRS_CH1_CTRL 0x018 PRS_CH2_CTRL 0x01C PRS_CH3_CTRL 0x020 PRS_CH4_CTRL 0x024 PRS_CH5_CTRL 0x028 PRS_CH6_CTRL 0x02C PRS_CH7_CTRL 13.5 Register ...
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PRS_SWLEVEL - Software Level Register Offset 0x004 Reset Access Name Bit Name Reset 31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 ( CH7LEVEL 0 See bit 0. ...
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Bit Name Reset Value Mode 2 LOC2 3 LOC3 7:4 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 ( CH3PEN 0 When set, GPIO output from PRS channel 3 ...
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Bit Name Reset Value Mode 0b010001 USART1 0b011100 TIMER0 0b011101 TIMER1 0b101000 RTC 0b110000 GPIOL 0b110001 GPIOH 0b110100 LETIMER0 0b111001 LESENSEL 0b111010 LESENSEH 0b111011 LESENSED 15:3 Reserved To ensure compatibility with future devices, always write bits to 0. More information ...
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Bit Name Reset Value Mode 0b000 RTCOF 0b001 RTCCOMP0 0b010 RTCCOMP1 SOURCESEL = 0b110000 (GPIO) 0b000 GPIOPIN0 0b001 GPIOPIN1 0b010 GPIOPIN2 0b011 GPIOPIN3 0b100 GPIOPIN4 0b101 GPIOPIN5 0b110 GPIOPIN6 0b111 GPIOPIN7 SOURCESEL = 0b110001 (GPIO) 0b000 GPIOPIN8 0b001 GPIOPIN9 0b010 ...
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Inter-Integrated Circuit Interface Other I C Other I m aster slave 14.1 Introduction 2 The I C module provides an interface between the MCU and a serial ...
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Functional Description 2 An overview of the I C module is shown in Figure 14.1 (p. 141 Figure 14. Overview I2Cn_SDA Pin ctrl I2Cn_SCL 2 14.3.1 I C-Bus Overview 2 The I C-bus uses two ...
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The GPIO drive strength can be used to control slew rate. 14.3.1.1 START and STOP Conditions START and STOP conditions are used to initiate and stop transactions on the I the bus begin with a START condition (S) and end ...
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Examples transfers are shown in Figure 14.5 (p. 143) , Figure 14.6 (p. 143) , and Figure 14.7 (p. 143) . The identifiers used are: • ADDR - Address • DATA - Data • ...
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When performing a master transmitter operation, the master transmits the two address bytes and then the remaining data, as shown in Figure 14.8 (p. 144 Figure 14. Master Transmitter/Slave Receiver with 10-bit Address S ADDR (1st ...
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I2Cn_CTRL must be reset. This should be done regardless of whether the slave is going to be re-enabled or not. 14.3.4 Clock Generation The SCL clock signal generated by the I The clock is generated as a division of the ...
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Buffers 14.3.6.1 Transmit Buffer and Shift Register 2 The I C transmitter is double buffered through the transmit buffer and transmit shift register as shown in Figure 14.1 (p. 141 byte is loaded into the transmit buffer ...
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After the address has been transmitted, a sequence of bytes can be read from or written to the slave, depending on the value of the R/W bit (bit 0 in the address byte). If the bit was cleared, the master ...
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Interactions 2 Whenever the I C module is waiting for interaction from software, it holds the bus clock SCL low, freezing all bus activities, and the BUSHOLD interrupt flag in I2Cn_IF is set. The action(s) required by software depends ...
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STATUS register. A pending START command can for instance be identified by PSTART having a high value. 2 Whenever the I C module requires an interaction, it checks the ...
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I2Cn_STATE will then be 0x57. As seen in the table, the I the address is not available after a repeated start condition. To continue, write a byte to I2Cn_TXDATA with the address of the slave in the 7 ...
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I2Cn_STATE Description - Data transmitted 0xD7 Data transmitted,ACK received 0xDF Data transmitted,NACK received - Stop transmitted - Arbitration lost 14.3.7.5 Master Receiver To receive data from a slave, the master must operate as a master receiver, see Table 14.5 (p. ...
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As when operating as a master transmitter, arbitration can be lost as a master receiver. When this happens the ARBLOST interrupt flag in I2Cn_IF is set, and the master has a possibility of being selected as a slave given the ...
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I2Cn_STATE Description - Arbitration lost 14.3.8 Bus States The I2Cn_STATE register can be used to determine which state the given time. The register consists of the STATE bit-field, which shows which state the any ...
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Slave State Machine The slave state machine is shown in Figure 14.11 (p. 154) . The dotted lines show where I interrupt flags are set. The full-drawn circles show places where interaction may be required by software to let ...
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After a START or repeated START condition, the bus master will transmit an address along with bit. If there is no room in the receive shift register for the address, the bus will be held by the ...
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Table 14. Slave Transmitter I2Cn_STATE Description 0x41 Repeated START received 0x73 ADDR + R received - Data transmitted 0xD5 Data transmitted, ACK received 0xDD Data transmitted, NACK received - Stop received - Arbitration lost 14.3.9.4 Slave Receiver ...
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See Table 14.9 (p. 157) for more information. 2 Table 14. Slave Receiver I2Cn_STATE Description - Repeated START received 0x71 ADDR + W received 0xB1 Data received - Stop received - Arbitration lost 14.3.10 Transfer Automation 2 ...
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Using 10-bit Addresses When using 10-bit addresses in slave mode, set the I2Cn_SADDR register to 1111 0XX where XX are the two most significant bits of the 10-bit address, and set I2Cn_SADDRMASK to 0xFF. Address matches will now be ...
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Many slave-only devices operating case that SCL is stuck LOW, the advice is to apply a hardware reset signal to the slaves on the bus. If this does not work, cycle the power to the devices in ...
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Transmit buffer and shift register empty. No data to send • Transmit buffer empty 14.3.14 Interrupts The interrupts generated by the I interrupts are enabled, an interrupt will be made if one or more of the interrupt flags in ...
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Register Map The offset register address is relative to the registers base address. Offset Name 0x000 I2Cn_CTRL 0x004 I2Cn_CMD 0x008 I2Cn_STATE 0x00C I2Cn_STATUS 0x010 I2Cn_CLKDIV 0x014 I2Cn_SADDR 0x018 I2Cn_SADDRMASK 0x01C I2Cn_RXDATA 0x020 I2Cn_RXDATAP 0x024 I2Cn_TXDATA 0x028 I2Cn_IF 0x02C I2Cn_IFS ...
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Bit Name Reset When set, the bus automatically goes idle on a bus idle timeout, allowing new transfers to be initiated. Value Description 0 A bus idle timeout has no effect on the bus state bus idle timeout ...
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Bit Name Reset Value Description 0 Software must give one ACK command for each ACK transmitted on the I 1 Addresses that are not automatically NACK'ed, and all data is automatically acknowledged. 1 SLAVE 0 Set this bit to allow ...
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I2Cn_STATE - State Register Offset 0x008 Reset Access Name Bit Name Reset 31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 7:5 STATE 0x0 The state of any ...
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Bit Name Reset 8 RXDATAV 0 Set when data is available in the receive buffer. Cleared when the receive buffer is empty. 7 TXBL 1 Indicates the level of the transmit buffer. Set when the transmit buffer is empty, and ...
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Bit Name Reset 31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 7:1 ADDR 0x00 Specifies the slave address of the device. 0 Reserved To ensure compatibility with future ...
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I2Cn_RXDATAP - Receive Buffer Data Peek Register Offset 0x020 Reset Access Name Bit Name Reset 31:8 Reserved To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3) 7:0 RXDATAP 0x00 Use ...
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Bit Name Reset Set on each clock low timeout. The timeout value can be set in CLTO bitfield in the I2Cn_CTRL register. 14 BITO 0 Set on each bus idle timeout. The timeout value can be set in the BITO ...
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Bit Name Reset 16 SSTOP 0 Write set the SSTOP interrupt flag. 15 CLTO 0 Write set the CLTO interrupt flag. 14 BITO 0 Write set the BITO interrupt flag. 13 ...
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Bit Name Reset Write clear the SSTOP interrupt flag. 15 CLTO 0 Write clear the CLTO interrupt flag. 14 BITO 0 Write clear the BITO interrupt flag. 13 RXUF 0 Write ...
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Bit Name Reset 15 CLTO 0 Enable interrupt on clock low timeout. 14 BITO 0 Enable interrupt on bus idle timeout. 13 RXUF 0 Enable interrupt on receive buffer underflow. 12 TXOF 0 Enable interrupt on transmit buffer overflow. 11 ...
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Bit Name Reset 10:8 LOCATION 0x0 2 Decides the location of the I C I/O pins. Value Mode 0 LOC0 1 LOC1 2 LOC2 3 LOC3 7:2 Reserved To ensure compatibility with future devices, always write bits to 0. More ...
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USART - Universal Synchronous Asynchronous Receiver/Transmitter DMA RAM controller USART RX/ MISO TX/ MOSI CLK CS EFM32 15.1 Introduction The Universal Synchronous Asynchronous serial Receiver and Transmitter (USART very flexible serial I/O ...
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Configurable number of data bits, 4-16 (plus the parity bit, if enabled) • HW parity bit generation and check • Configurable number of stop bits in asynchronous mode: 0.5, 1, 1.5, 2 • HW collision detection • Multi-processor mode ...
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Asynchronous or synchronous mode can be selected by configuring SYNC in USARTn_CTRL. The options are listed with supported protocols in Table ...
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Table 15.3. USART Data Bits DATA BITS [3:0] 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 Table 15.4. USART Stop Bits STOP BITS [1: The order in which the data bits ...
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Table 15.5. USART Parity Bits STOP BITS [1: 15.3.2.2 Clock Generation The USART clock defines the transmission and reception data rate. When operating in asynchronous mode, the baud rate (bit-rate) is given by Equation 15.1 (p. ...
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Table 15.7. USART Baud Rates @ 4MHz Peripheral Clock USARTn_OVS =00 Desired baud rate USARTn_CLKDIV/256 [baud/s] 600 415,75 1200 207,25 2400 103,25 4800 51 9600 25 14400 16,25 19200 12 28800 7,75 38400 5,5 57600 3,25 76800 2,25 115200 1,25 ...
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When data is written to the transmit buffer using USARTn_TXDATAX and USARTn_TXDOUBLEX, the 9th bit(s) written to these registers override the value in BIT8DV in USARTn_CTRL, and alone define the ...
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Note When in SmartCard mode with repeat enabled, none of the actions, except generate break, will be performed until the frame is transmitted without failure. Generation of a break in SmartCard mode with repeat enabled will cause the USART to ...
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Figure 15.4. USART Receive Buffer Operation RXDOUBLE RXDOUBLEX RX buffer elem ent 0 RXDOUBLEXP RX buffer elem ent 1 Shift register The receive buffer, including the receive shift register can be cleared by setting CLEARRX in USARTn_CMD. Any frame currently ...
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OVS=1 and locations 3, 4, and 5 for OVS=2. The value of a sampled bit is determined by majority vote. If two or more of the ...
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When working with stop bit lengths of half a baud period, the above sampling scheme no longer suffices. In this case, the stop-bit is not sampled, and no framing error is generated in the receiver if the stop- bit is ...
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Single Data-link In this setup, the USART both receives and transmits data on the same pin. This is enabled by setting LOOPBK in USARTn_CTRL, which connects the receiver to the transmitter output. Because they are both connected to the ...
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The USn_CS output is active low by default, but its polarity can be changed with CSINV in USARTn_CTRL. AUTOCS works regardless of which mode the USART is in, so this functionality can also be used for automatic chip/slave select when ...
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Figure 15.10. USART Transmission of Large Frames, MSBF TX buffer elem ent 1 TX buffer elem ent Figure 15.10 (p. 186) illustrates the order of the transmitted bits when an 11 bit frame ...
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MPAF interrupt flag in USARTn_IF is set, and the address frame is loaded into the receive register. This happens regardless of the value of RXBLOCK in USARTn_STATUS. Multi-processor mode is enabled by setting MPM in USARTn_CTRL, and the value of ...
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USARTn_CTRL or through an external connection. The TX output should be configured as open-drain in the GPIO module. When no parity error is identified by the receiver, the data frame is as shown in Figure 15.12 (p. 188) . The ...
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Figure 15.14. USART SmartCard Stop Bit Sampling 1/2 stop bit For communication with a SmartCard, a clock signal needs to be generated ...
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USARTn_CLKDIV = 256 x (f When the USART operates in master mode, the highest possible bit rate is half the peripheral clock rate. When operating in slave mode however, the highest bit rate is an eight of the peripheral clock: ...
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When there are no more frames in the transmit buffer and the transmit shift register is empty, the clock stops, and communication ends. When the receiver is enabled, it samples data using the internal clock when the transmitter transmits data. ...
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Synchronous Half Duplex Communication Half duplex communication in synchronous mode is very similar to half duplex communication in asynchronous mode as detailed in Section 15.3.2.6 (p. 183) . The main difference is that in this mode, the master must ...
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The regular I2S waveform is shown in Figure 15.16 (p. 193) and Figure 15.17 (p. 193) . The first figure shows a waveform transmitted with full accuracy. The wordlength can be configured to 32-bit, 16-bit or 8-bit using FORMAT in ...
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Figure 15.19. USART Right-justified I2S waveform USn_CLK USn_TX/ LSB USn_RX Right channel In mono-mode, the word-select signal pulses at the beginning of each word instead of toggling for each word. Mono I2S waveform is shown in Figure 15.20 (p. 194) ...
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USARTn_TRIGCTRL is set, and the transmitter is enabled if TXTEN in USARTn_TRIGCTRL is set. Only one signal input is supported by the USART. The AUTOTX feature can also be enabled via PRS external SPI device sets a ...
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Using the transmission delay, a transmission can be started when a frame is received, and it is possible to make sure that the transmitter does not begin driving the output before the frame on the bus is completely ...
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The IrDA module is enabled by setting IREN. The USART transmitter output and receiver input is then routed through the IrDA modulator. The width of the pulses generated by the IrDA modulator is set by configuring IRPW in USARTn_IRCTRL. Four ...
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Register Map The offset register address is relative to the registers base address. Offset Name 0x000 USARTn_CTRL 0x004 USARTn_FRAME 0x008 USARTn_TRIGCTRL 0x00C USARTn_CMD 0x010 USARTn_STATUS 0x014 USARTn_CLKDIV 0x018 USARTn_RXDATAX 0x01C USARTn_RXDATA 0x020 USARTn_RXDOUBLEX 0x024 USARTn_RXDOUBLE 0x028 USARTn_RXDATAXP 0x02C USARTn_RXDOUBLEXP ...
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Bit Name Reset Transmits as long not full empty, underflows are generated. 28 BYTESWAP 0 Set to switch the order of the bytes in double accesses. Value Description 0 Normal byte order 1 Byte ...
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Bit Name Reset Default value is active low. This affects both the selection of external slaves, as well as the selection of the microcontroller as a slave. Value Description 0 Chip select is active low 1 Chip select is active ...