EFM32TG210F32 Energy Micro, EFM32TG210F32 Datasheet - Page 203

• Manufacturer Part Number: EFM32TG210F32
• Description: MCU 32BIT 32KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Tiny Geckor

Specifications of EFM32TG210F32

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: UART, I2C, SPI
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 17
• Number Of Timers: 1
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Processor To Be Evaluated: EFM32TG210
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

15.5.4 USARTn_CMD - Command Register
31:12
11
10
9
8
7
6
5
4
3
2
1
Bit
Offset
0x00C
Reset
Access
Name
Bit
2010-12-21 - d0034_Rev0.90
Select USART PRS trigger channel. The PRS signal can enable RX and/or TX, depending on the setting of RXTEN and TXTEN.
Reserved
CLEARRX
Set to clear receive buffer and the RX shift register.
CLEARTX
Set to clear transmit buffer and the TX shift register.
TXTRIDIS
Disables tristating of the transmitter output.
TXTRIEN
Tristates the transmitter output.
RXBLOCKDIS
Set to clear RXBLOCK, resulting in all incoming frames being loaded into the receive buffer.
RXBLOCKEN
Set to set RXBLOCK, resulting in all incoming frames being discarded.
MASTERDIS
Set to disable master mode, clearing the MASTER status bit and putting the USART in slave mode.
MASTEREN
Set to enable master mode, setting the MASTER status bit. Master mode should not be enabled while TXENS is set to 1. To enable
both master and TX mode, write MASTEREN before TXEN, or enable them both in the same write operation.
TXDIS
Set to disable transmission.
TXEN
Set to enable data transmission.
RXDIS
Set to disable data reception. If a frame is under reception when the receiver is disabled, the incoming frame is discarded.
Name
Name
Value
0
1
2
3
4
5
6
7
Mode
PRSCH0
PRSCH1
PRSCH2
PRSCH3
PRSCH4
PRSCH5
PRSCH6
PRSCH7
0
0
0
0
0
0
0
0
0
0
0
Reset
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
W1
W1
W1
W1
W1
W1
W1
W1
W1
W1
W1
Access
Access
Description
PRS Channel 0 selected
PRS Channel 1 selected
PRS Channel 2 selected
PRS Channel 3 selected
PRS Channel 4 selected
PRS Channel 5 selected
PRS Channel 6 selected
PRS Channel 7 selected
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203
Bit Position
Clear RX
Clear TX
Transmitter Tristate Disable
Transmitter Tristate Enable
Receiver Block Disable
Receiver Block Enable
Master Disable
Master Enable
Transmitter Disable
Transmitter Enable
Receiver Disable
Description
Description
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