EFM32TG210F32 Energy Micro, EFM32TG210F32 Datasheet - Page 198

• Manufacturer Part Number: EFM32TG210F32
• Description: MCU 32BIT 32KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Tiny Geckor

Specifications of EFM32TG210F32

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: UART, I2C, SPI
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 17
• Number Of Timers: 1
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Processor To Be Evaluated: EFM32TG210
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

15.4 Register Map
15.5 Register Description
15.5.1 USARTn_CTRL - Control Register
31
30
29
Offset
0x000
0x004
0x008
0x00C
0x010
0x014
0x018
0x01C
0x020
0x024
0x028
0x02C
0x030
0x034
0x038
0x03C
0x040
0x044
0x048
0x04C
0x050
0x054
0x058
0x05C
Offset
0x000
Reset
Access
Name
Bit
2010-12-21 - d0034_Rev0.90
The offset register address is relative to the registers base address.
Reserved
MVDIS
Disable majority vote for 16x, 8x and 6x oversampling modes.
AUTOTX
Name
Name
USARTn_CTRL
USARTn_FRAME
USARTn_TRIGCTRL
USARTn_CMD
USARTn_STATUS
USARTn_CLKDIV
USARTn_RXDATAX
USARTn_RXDATA
USARTn_RXDOUBLEX
USARTn_RXDOUBLE
USARTn_RXDATAXP
USARTn_RXDOUBLEXP
USARTn_TXDATAX
USARTn_TXDATA
USARTn_TXDOUBLEX
USARTn_TXDOUBLE
USARTn_IF
USARTn_IFS
USARTn_IFC
USARTn_IEN
USARTn_IRCTRL
USARTn_ROUTE
USARTn_INPUT
USARTn_I2SCTRL
0
0
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
RW
RW
Access
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198
Bit Position
Type
RW
RW
RW
W1
R
RW
R
R
R
R
R
R
W
W
W
W
R
W1
W1
RW
RW
RW
RW
RW
Majority Vote Disable
Always Transmit When RX Not Full
Description
Description
Control Register
USART Frame Format Register
USART Trigger Control register
Command Register
USART Status Register
Clock Control Register
RX Buffer Data Extended Register
RX Buffer Data Register
RX Buffer Double Data Extended Register
RX FIFO Double Data Register
RX Buffer Data Extended Peek Register
RX Buffer Double Data Extended Peek Register
TX Buffer Data Extended Register
TX Buffer Data Register
TX Buffer Double Data Extended Register
TX Buffer Double Data Register
Interrupt Flag Register
Interrupt Flag Set Register
Interrupt Flag Clear Register
Interrupt Enable Register
IrDA Control Register
I/O Routing Register
USART Input Register
I2S Control Register
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