EFM32TG210F32 Energy Micro, EFM32TG210F32 Datasheet - Page 38

• Manufacturer Part Number: EFM32TG210F32
• Description: MCU 32BIT 32KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Tiny Geckor

Specifications of EFM32TG210F32

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: UART, I2C, SPI
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 17
• Number Of Timers: 1
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Processor To Be Evaluated: EFM32TG210
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

7.5.8 MSC_IF - Interrupt Flag Register
31:7
6
5
4
3
2
1
0
31:4
3
2
1
0
Bit
Offset
0x02C
Reset
Access
Name
Bit
2010-12-21 - d0034_Rev0.90
Reserved
PCRUNNING
This bit is set while the performance counters are running. When one performance counter reaches the maximum value, this bit
is cleared.
ERASEABORTED
When set, the current erase operation was aborted by interrupt.
WORDTIMEOUT
When this bit is set, MSC_WDATA was not written within the timeout. The flash write operation timed out and access to the
flash is returned to the AHB interface. This bit is cleared when the ERASEPAGE, WRITETRIG or WRITEONCE commands in
MSC_WRITECMD are triggered.
WDATAREADY
When this bit is set, the content of MSC_WDATA is read by MSC Flash Write Controller and the register may be updated with the
next 32-bit word to be written to flash. This bit is cleared when writing to MSC_WDATA.
INVADDR
Set when software attempts to load an invalid (unmapped) address into ADDR
LOCKED
When set, the last erase or write is aborted due to erase/write access constraints
BUSY
When set, an erase or write operation is in progress and new commands are ignored
Reserved
CMOF
Set when MSC_CACHEMISSES overflows
CHOF
Set when MSC_CACHEHITS overflows
WRITE
Set when a write is done
ERASE
Set when erase is done
Name
Name
0
0
0
1
0
0
0
0
0
0
0
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
R
R
R
R
R
R
R
R
R
R
R
Access
Access
...the world's most energy friendly microcontrollers
Bit Position
38
Performance Counters Running
The Current Flash Erase Operation Aborted
Flash Write Word Timeout
WDATA Write Ready
Invalid Write Address or Erase Page
Access Locked
Erase/Write Busy
Cache Misses Overflow Interrupt Flag
Cache Hits Overflow Interrupt Flag
Write Done Interrupt Read Flag
Erase Done Interrupt Read Flag
Description
Description
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