EFM32TG210F32 Energy Micro, EFM32TG210F32 Datasheet - Page 46

• Manufacturer Part Number: EFM32TG210F32
• Description: MCU 32BIT 32KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Tiny Geckor

Specifications of EFM32TG210F32

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: UART, I2C, SPI
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 17
• Number Of Timers: 1
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Processor To Be Evaluated: EFM32TG210
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

8.4.2.2 Priority
2010-12-21 - d0034_Rev0.90
Table 8.1 (p. 46) lists the arbitration rates.
Table 8.1. AHB bus transfer arbitration interval
Note
When N > 2
transfers until N < 2
end of the DMA cycle.
You store the value of the R_power bits in the channel control data structure. See Section 8.4.3.3 (p.
58) for more information about the location of the R_power bits in the data structure.
When the controller arbitrates, it determines the next channel to service by using the following
information:
• the channel number
• the priority level, default or high, that is assigned to the channel.
You can configure each channel to use either the default priority level or a high priority level by setting
the DMA_CHPRIS register.
Channel number zero has the highest priority and as the channel number increases, the priority of a
channel decreases. Table 8.2 (p. 46) lists the DMA channel priority levels in descending order of
priority.
Table 8.2. DMA channel priority
R_power
b0000
b0001
b0010
b0011
b0100
b0101
b0110
b0111
b1000
b1001
b1010 - b1111
Channel
number
3
0
1
2
You must take care not to assign a low-priority channel with a large R_power because this
prevents the controller from servicing high-priority requests, until it rearbitrates.
Priority level
setting
High
High
High
High
R
Arbitrate after x DMA transfers
x = 1
x = 2
x = 4
x = 8
x = 16
x = 32
x = 64
x = 128
x = 256
x = 512
x = 1024
and is not an integer multiple of 2
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remain to be transferred. The controller performs the remaining N transfers at the
Descending order of
channel priority
Highest-priority DMA channel
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-
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46
then the controller always performs sequences of 2
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