EFM32TG210F32 Energy Micro, EFM32TG210F32 Datasheet - Page 201

• Manufacturer Part Number: EFM32TG210F32
• Description: MCU 32BIT 32KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Tiny Geckor

Specifications of EFM32TG210F32

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: UART, I2C, SPI
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 17
• Number Of Timers: 1
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Processor To Be Evaluated: EFM32TG210
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

15.5.2 USARTn_FRAME - USART Frame Format Register
4
3
2
1
0
31:14
13:12
Bit
Offset
0x004
Reset
Access
Name
Bit
2010-12-21 - d0034_Rev0.90
MPAB
Defines the value of the multi-processor address bit. An incoming frame with its 9th bit equal to the value of this bit marks the frame
as a multi-processor address frame.
MPM
Multi-processor mode uses the 9th bit of the USART frames to tell whether the frame is an address frame or a data frame.
CCEN
Enables collision checking on data when operating in half duplex modus.
LOOPBK
Allows the receiver to be connected directly to the USART transmitter for loopback and half duplex communication.
SYNC
Determines whether the USART is operating in asynchronous or synchronous mode.
Reserved
STOPBITS
Determines the number of stop-bits used.
Name
Name
Value
1
2
3
Value
0
1
Value
0
1
Value
0
1
Value
0
1
Value
0
1
2
Mode
X8
X6
X4
Mode
HALF
ONE
ONEANDAHALF
Description
The 9th bit of incoming frames has no special function
An incoming frame with the 9th bit equal to MPAB will be loaded into the receive buffer regardless of RXBLOCK and
will result in the MPAB interrupt flag being set
Description
Collision check is disabled
Collision check is enabled. The receiver must be enabled for the check to be performed
Description
The receiver is connected to and receives data from U(S)n_RX
The receiver is connected to and receives data from U(S)n_TX
Description
The USART operates in asynchronous mode
The USART operates in synchronous mode
0
0
0
0
0
0x1
Reset
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
RW
RW
RW
RW
RW
RW
Access
Access
Description
Double speed with 8X oversampling in asynchronous mode
6X oversampling in asynchronous mode
Quadruple speed with 4X oversampling in asynchronous mode
Description
The transmitter generates a half stop bit. Stop-bits are not verified by receiver
One stop bit is generated and verified
The transmitter generates one and a half stop bit. The receiver verifies the first stop bit
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201
Bit Position
Multi-Processor Address-Bit
Multi-Processor Mode
Collision Check Enable
Loopback Enable
USART Synchronous Mode
Stop-Bit Mode
Description
Description
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