EFM32TG210F32 Energy Micro, EFM32TG210F32 Datasheet - Page 141

• Manufacturer Part Number: EFM32TG210F32
• Description: MCU 32BIT 32KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Tiny Geckor

Specifications of EFM32TG210F32

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: UART, I2C, SPI
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 17
• Number Of Timers: 1
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Processor To Be Evaluated: EFM32TG210
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

14.3 Functional Description
14.3.1 I
2010-12-21 - d0034_Rev0.90
An overview of the I
Figure 14.1. I
The I
shown in Figure 14.2 (p. 141) . As a true multi-master bus it includes collision detection and arbitration
to resolve situations where multiple masters transmit data at the same time without data loss.
Figure 14.2. I
Each device on the bus is addressable by a unique address, and an I
devices on the bus, including other masters.
Both the bus lines are open-drain. The maximum value of the pull-up resistor can be calculated as a
function of the maximal rise-time tr for the given bus speed, and the estimated bus capacitance Cb as
shown in Equation 14.1 (p. 141) .
I
The maximal rise times for 100 kHz, 400 kHz and 1 MHz I
Note
2
C Pull-up Resistor Equation
2
C-bus uses two wires for communication; a serial data line (SDA) and a serial clock line (SCL) as
2
C-Bus Overview
SDA
SCL
I2Cn_SDA
I2Cn_SCL
2
2
C Overview
C-Bus Example
I
2
C m aster
2
# 1
C module is shown in Figure 14.1 (p. 141) .
Pin
ctrl
I
2
C m aster
# 2
Rp(max) = tr/0.8473 x Cb
I
2
C Control and
Recognizer
Generator
Controller
Receive
Address
Sym bol
Status
I
2
C slave
# 1
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141
Clock generator
Peripheral Bus
Transm it Buffer
I
Shift Register
2
C slave
Transm it
2
# 2
C are 1 µs, 300 ns and 120 ns respectively.
I
2
C slave
# 3
2
C master can address all the
V
DD
Receive Buffer
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Shift Register
Receive
R
p
(14.1)