ATMEGA64RZAV-10PU Atmel, ATMEGA64RZAV-10PU Datasheet - Page 82

• Manufacturer Part Number: ATMEGA64RZAV-10PU
• Description: MCU ATMEGA644/AT86RF230 40-DIP
• Manufacturer: Atmel
• Series: ATMEGAr

Specifications of ATMEGA64RZAV-10PU

• Frequency: 2.4GHz
• Modulation Or Protocol: 802.15.4 Zigbee
• Power - Output: 3dBm
• Sensitivity: -101dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Data Interface: PCB, Surface Mount
• Memory Size: 64kB Flash, 2kB EEPROM, 4kB RAM
• Antenna Connector: PCB, Surface Mount
• Package / Case: 40-DIP (0.600", 15.24mm)
• Wireless Frequency: 2.4 GHz
• Interface Type: JTAG, SPI
• Output Power: 3 dBm
• For Use With: ATSTK600-TQFP32 - STK600 SOCKET/ADAPTER 32-TQFPATAVRISP2 - PROGRAMMER AVR IN SYSTEMATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Applications: -
• Data Rate - Maximum: -
• Current - Transmitting: -
• Current - Receiving: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: ATmega64

82
ATmega644
• INT0/PCINT26 – Port D, Bit 2
INT0, External Interrupt source 0. The PD2 pin can serve as an external interrupt source to the
MCU.
PCINT26, Pin Change Interrupt Source 26: The PD2 pin can serve as an external interrupt
source.
• TXD0/PCINT25 – Port D, Bit 1
TXD0, Transmit Data (Data output pin for the USART0). When the USART0 Transmitter is
enabled, this pin is configured as an output regardless of the value of DDD1.
PCINT25, Pin Change Interrupt Source 25: The PD1 pin can serve as an external interrupt
source.
• RXD0/PCINT24 – Port D, Bit 0
RXD0, Receive Data (Data input pin for the USART0). When the USART0 receiver is enabled
this pin is configured as an input regardless of the value of DDD0. When the USART forces this
pin to be an input, the pull-up can still be controlled by the PORTD0 bit.
PCINT24, Pin Change Interrupt Source 24: The PD0 pin can serve as an external interrupt
source.
Table 12-13
shown in
Table 12-13. Overriding Signals for Alternate Functions PD7:PD4
Signal Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
DIEOE
DIEOV
DI
AIO
Figure 12-5 on page
and
Table 12-14
PD7/OC2A/
PCINT31
0
0
0
0
OC2A ENABLE
OCA2A
PCINT31 • PCIE3
1
PCINT31 INPUT
–
relates the alternate functions of Port D to the overriding signals
71.
PD6/ICP1/
OC2B/
PCINT30
0
0
0
0
OC2B ENABLE
OC2B
PCINT30 • PCIE3
1
ICP1 INPUT
PCINT30 INPUT
–
PD5/OC1A/
PCINT29
0
0
0
0
OC1A ENABLE
OC1A
PCINT29 • PCIE3
1
PCINT29 INPUT
–
PD4/OC1B/
PCINT28
0
0
0
0
OC1B ENABLE
OC1B
PCINT28 • PCIE3
1
PCINT28 INPUT
–
2593N–AVR–07/10