ATMEGA64RZAV-10PU Atmel, ATMEGA64RZAV-10PU Datasheet - Page 167

• Manufacturer Part Number: ATMEGA64RZAV-10PU
• Description: MCU ATMEGA644/AT86RF230 40-DIP
• Manufacturer: Atmel
• Series: ATMEGAr

Specifications of ATMEGA64RZAV-10PU

• Frequency: 2.4GHz
• Modulation Or Protocol: 802.15.4 Zigbee
• Power - Output: 3dBm
• Sensitivity: -101dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Data Interface: PCB, Surface Mount
• Memory Size: 64kB Flash, 2kB EEPROM, 4kB RAM
• Antenna Connector: PCB, Surface Mount
• Package / Case: 40-DIP (0.600", 15.24mm)
• Wireless Frequency: 2.4 GHz
• Interface Type: JTAG, SPI
• Output Power: 3 dBm
• For Use With: ATSTK600-TQFP32 - STK600 SOCKET/ADAPTER 32-TQFPATAVRISP2 - PROGRAMMER AVR IN SYSTEMATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Applications: -
• Data Rate - Maximum: -
• Current - Transmitting: -
• Current - Receiving: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: ATmega64

17.3.2
17.3.3
2593N–AVR–07/10
Double Speed Operation (U2Xn)
External Clock
Table 17-1.
Some examples of UBRRn values for some system clock frequencies are found in
page
The transfer rate can be doubled by setting the U2Xn bit in UCSRnA. Setting this bit only has
effect for the asynchronous operation. Set this bit to zero when using synchronous operation.
Setting this bit will reduce the divisor of the baud rate divider from 16 to 8, effectively doubling
the transfer rate for asynchronous communication. Note however that the Receiver will in this
case only use half the number of samples (reduced from 16 to 8) for data sampling and clock
recovery, and therefore a more accurate baud rate setting and system clock are required when
this mode is used. For the Transmitter, there are no downsides.
External clocking is used by the synchronous slave modes of operation. The description in this
section refers to
Operating Mode
Asynchronous Normal
mode (U2Xn = 0)
Asynchronous Double
Speed mode (U2Xn = 1)
Synchronous Master
mode
187.
BAUD
f
UBRRn
OSC
Equations for Calculating Baud Rate Register Setting
Figure 17-2
Baud rate (in bits per second, bps)
System Oscillator clock frequency
Contents of the UBRRHn and UBRRLn Registers, (0-4095)
for details.
Equation for Calculating Baud
BAUD
BAUD
BAUD
=
=
=
----------------------------------------- -
16 UBRRn
Rate
-------------------------------------- -
8 UBRRn
-------------------------------------- -
2 UBRRn
(
(
(
(1)
f
f
f
OSC
OSC
OSC
+
+
+
1
1
1
)
)
)
UBRRn
UBRRn
UBRRn
Equation for Calculating UBRR
=
=
=
ATmega644
----------------------- - 1
16BAUD
------------------- - 1
8BAUD
------------------- - 1
2BAUD
Value
f
f
f
OSC
OSC
OSC
Table 17-9 on
–
–
–
167