ATMEGA64RZAV-10PU Atmel, ATMEGA64RZAV-10PU Datasheet - Page 233

• Manufacturer Part Number: ATMEGA64RZAV-10PU
• Description: MCU ATMEGA644/AT86RF230 40-DIP
• Manufacturer: Atmel
• Series: ATMEGAr

Specifications of ATMEGA64RZAV-10PU

• Frequency: 2.4GHz
• Modulation Or Protocol: 802.15.4 Zigbee
• Power - Output: 3dBm
• Sensitivity: -101dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Data Interface: PCB, Surface Mount
• Memory Size: 64kB Flash, 2kB EEPROM, 4kB RAM
• Antenna Connector: PCB, Surface Mount
• Package / Case: 40-DIP (0.600", 15.24mm)
• Wireless Frequency: 2.4 GHz
• Interface Type: JTAG, SPI
• Output Power: 3 dBm
• For Use With: ATSTK600-TQFP32 - STK600 SOCKET/ADAPTER 32-TQFPATAVRISP2 - PROGRAMMER AVR IN SYSTEMATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Applications: -
• Data Rate - Maximum: -
• Current - Transmitting: -
• Current - Receiving: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: ATmega64

21. Analog-to-digital Converter
21.1
21.2
2593N–AVR–07/10
Features
Overview
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Note:
The ATmega644 features a 10-bit successive approximation ADC. The ADC is connected to an
8-channel Analog Multiplexer which allows 8 single-ended voltage inputs constructed from the
pins of Port A. The single-ended voltage inputs refer to 0V (GND).
The device also supports 16 differential voltage input combinations. Two of the differential inputs
(ADC1, ADC0 and ADC3, ADC2) are equipped with a programmable gain stage, providing
amplification steps of 0 dB (1x), 20 dB (10x), or 46 dB (200x) on the differential input voltage
before the A/D conversion. Seven differential analog input channels share a common negative
terminal (ADC1), while any other ADC input can be selected as the positive input terminal. If 1x
or 10× gain is used, 8-bit resolution can be expected. If 200x gain is used, 7-bit resolution can be
expected.
The ADC contains a Sample and Hold circuit which ensures that the input voltage to the ADC is
held at a constant level during conversion. A block diagram of the ADC is shown in
The ADC has a separate analog supply voltage pin, AVCC. AVCC must not differ more than
±0.3V from V
pin.
Internal reference voltages of nominally 1.1V, 2.56V or AVCC are provided On-chip. The voltage
reference may be externally decoupled at the AREF pin by a capacitor for better noise
performance.
10-bit Resolution
0.5 LSB Integral Non-linearity
±2 LSB Absolute Accuracy
65 µs - 260 µs Conversion Time
Up to 15 kSPS at Maximum Resolution
8 Multiplexed Single Ended Input Channels
Differential mode with selectable gain at 1x, 10x or 200x
Optional Left adjustment for ADC Result Readout
0V - V
2.7V - V
Selectable 2.56V or 1.1V ADC Reference Voltage
Free Running or Single Conversion Mode
ADC Start Conversion by Auto Triggering on Interrupt Sources
Interrupt on ADC Conversion Complete
Sleep Mode Noise Canceler
CC
1. The differential input channels are not tested for devices in PDIP Package. This feature is only
CC
ADC Input Voltage Range
guaranteed to work for devices in TQFP and QFN/MLF Packages.
Differential ADC Voltage Range
CC
. See the paragraph
”ADC Noise Canceler” on page 241
on how to connect this
ATmega644
Figure
21-1.
233