ATMEGA64RZAV-10PU Atmel, ATMEGA64RZAV-10PU Datasheet
ATMEGA64RZAV-10PU
Specifications of ATMEGA64RZAV-10PU
Related parts for ATMEGA64RZAV-10PU
ATMEGA64RZAV-10PU Summary of contents
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Features • High Performance RF-CMOS 2.4 GHz Radio Transceiver Targeted for IEEE ® 802.15.4™, ZigBee , 6LoWPAN, RF4CE, SP100, WirelessHART™ and ISM Applications • Industry Leading Link Budget (104 dB): - Programmable Output Power from -17 dBm ...
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... Industrial control, sensing and automation (SP100, WirelessHART) • Home and building automation • Consumer electronics • PC peripherals The AT86RF230 can be operated by using an external microcontroller like ATMEL’s AVR microcontrollers. A comprehensive software programming description can be found in the application note AVR2009 “AT86RF230 – Software Programming Model”. 24 ...
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General Circuit Description Figure 3-1. Block Diagram of the AT86RF230 FTN AVREG BATMON RFP RFN I LNA PPF Q 5131E-MCU Wireless-02/09 This single-chip radio transceiver provides a complete radio transceiver interface between the antenna and the microcontroller. It comprises ...
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Pin Description Table 4-1. AT86RF230 Pin List Number Name 1 AVSS 2 AVSS 3 AVSS 4 RFP 5 RFN 6 AVSS 7 TST 8 RST 9 DVSS 10 DVSS 11 SLP_TR 12 DVSS 13 DVDD 14 DVDD 15 DEVDD ...
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Analog and RF Pins 5131E-MCU Wireless-02/09 AVDD, DVDD AVDD and DVDD are outputs of the internal 1.8V voltage regulators. The voltage regulators are controlled independently by the radio transceivers state machine and are activated depending on the current radio ...
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Table 4-2. Comments on Analog and RF Pins Pin Condition RFP/RFN VDC = 0.9V (TX) VDC = 20 mV (RX) at both pins XTAL1/XTAL2 CPAR = 3 pF VDC = 0.9V at both pins 4.3 Digital Pins 4.3.1 Driver Strength ...
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Pull-up and Pull-down Configuration of Digital Input Pins 4.3.3 Register Description 5131E-MCU Wireless-02/09 Pulling resistors are internally connected to all digital input pins in radio transceiver state P_ON (see section 7.1.2). Table 4-4 summarizes the pull-up and pull-down configuration. ...
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Application Circuit AT86RF230 8 Table 4-6. CLKM Driver Strength Register Bit Value PAD_IO_CLKM • Bit 3 – CLKM_SHA_SEL Refer to section 9.6.5. • Bit [2:0] – CLKM_CTRL Refer to section 9.6.5. An application circuit of ...
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Table 5-1. Example Bill of Materials Designator Description B1 SMD balun B1 SMD balun / filter (alternatively) CB1 LDO VREG bypass capacitor CB2 Power supply decoupling CB3 LDO VREG bypass capacitor CB4 Power supply decoupling CX1 Crystal load capacitor CX2 ...
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... SLP_TR RST GPIO4 Microcontrollers with a master SPI, such as Atmel’s AVR family, interface directly to the AT86RF230. The SPI is used for Frame Buffer and register access. The additional control signals are connected to the GPIO/IRQ interface of the microcontroller. Table 6-1 introduces the radio transceiver I/O signals and their functionality. ...
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SPI Timing Description Figure 6-2. SPI Timing, Global Map and Definition of Timing Parameters t Figure 6-3. SPI Timing, Detailed View and Definition of Timing Parameters t SEL SCLK MOSI Bit ...
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SPI Protocol Table 6-2. SPI Command Byte Definition Bit 7 Bit 6 Bit 5 Bit 6.2.1 Register Access Mode AT86RF230 12 master ...
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Figure 6-6. Example SPI Sequence - Register Access Mode Register Write Access SEL SCLK MOSI WRITE COMMAND MISO XX 6.2.2 Frame Buffer Access Modes Figure 6-7. Packet Structure - Frame Buffer Write Access 5131E-MCU Wireless-02/09 Figure 6-5. Packet Structure – ...
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Figure 6-8. Packet Structure - Frame Buffer Read Access Figure 6-9. Example SPI Sequence - Frame Buffer Write Sequence of a Frame with 4-byte PSDU SEL SCLK MOSI COMMAND MISO XX Figure 6-10. Example SPI Sequence - Frame Buffer Read ...
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Figure 6-11. Packet Structure - SRAM Write Access Figure 6-12. Packet Structure - SRAM Read Access Figure 6-13. Example SPI Sequence – SRAM Write Access Sequence byte Data Package SEL SCLK MOSI COMMAND ADDRESS MISO XX 5131E-MCU ...
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Figure 6-14. Example SPI Sequence – SRAM Read Access Sequence byte Data Package SEL SCLK MOSI COMMAND ADDRESS MISO XX 6.3 Radio Transceiver Identification 6.3.1 Register Description AT86RF230 DATA 1 DATA 2 Notes: ...
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... The SLP_TR signal is a multi-functional pin. Its function relates to the current state of the AT86RF230 and is summarized in Table 6-7. The radio transceiver states are explained in detail in section 7. AT86RF230 Description AT86RF230 Revision A AT86RF230 Revision MAN_ID_0 Description Atmel JEDEC manufacturer ID Bits [7: bit manufacturer ID MAN_ID_1 Description Atmel JEDEC manufacturer ID Bits [15: bit manufacturer ID MAN_ID_0 MAN_ID_1 17 ...
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Table 6-7. SLP_TR Multi-Functional Pin Radio Transceiver Status Function TRX_OFF Sleep SLEEP Wakeup RX_ON Disable CLKM RX_ON_NOCLK Enables CLKM RX_AACK_ON Disable CLKM RX_AACK_ON_NOCLK Enables CLKM PLL_ON TX start TX_ARET_ON TX start Figure 6-15. Sleep and Wake-up Initiated by Asynchronous Microcontroller ...
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Figure 6-16. Wake-Up Initiated by Radio Transceiver Interrupt CLKM 35 main clock cycles SLP_TR IRQ 6.5 Interrupt Logic 6.5.1 Overview Table 6-8. Interrupt Description in Basic Operating Mode IRQ Name Comments IRQ_7: BAT_LOW Indicates a supply voltage below the programmed ...
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Register Description AT86RF230 20 Register 0x0E (IRQ_MASK) The IRQ_MASK register is used to enable (set register bit disable (set register bit to 0) interrupt events by writing the corresponding bit to the interrupt mask register. Bit ...
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Operating Modes 7.1 Basic Operating Mode Figure 7-1. Basic Operating Mode State Diagram (for State Transition Timing Data Refer to Table 7-1) 7.1.1 State Control 5131E-MCU Wireless-02/09 This section summarizes all states to provide the basic functionality of the ...
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Basic Operating Mode Description 7.1.2.1 P_ON - Power-on after V 7.1.2.2 SLEEP – Sleep State AT86RF230 22 The pin SLP_TR is a multifunctional pin. Depending on radio transceiver state the rising edge of SLP_TR causes the following state transitions: ...
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TRX_OFF – Clock State 7.1.2.4 PLL_ON – PLL State 7.1.2.5 RX_ON and BUSY_RX – RX Listen and Receive State 7.1.2.6 RX_ON_NOCLK – RX Listen State without CLKM 5131E-MCU Wireless-02/09 Setting SLP_TR = L returns the radio transceiver to the ...
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BUSY_TX – Transmit State 7.1.3 Interrupt Handling in Basic Operating Mode AT86RF230 24 reception of a frame is indicated to the microcontroller by a RX_START interrupt. CLKM is turned on again, and the radio transceiver enters the BUSY_RX state ...
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Figure 7-2. Timing of RX_START and TRX_END Interrupts in Basic Operating Mode (see register 0x0F) -16 TRX_STATE PLL_ON SLP_TR IRQ Typ. Processing Delay Number of Octets Frame Content TRX_STATE IRQ Typ. Processing Delay 7.1.4 Basic Mode Timing 7.1.4.1 Power-on and ...
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Reset Procedure 7.1.4.3 State Transition Timing Table 7-1. State Transition Timing No Symbol Transition 1 t P_ON → TR1 2 t SLEEP → TR2 3 t TRX_OFF → TR3 4 t TRX_OFF → TR4 AT86RF230 26 In TRX_OFF state, ...
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No Symbol Transition 5 t PLL_ON → TR5 6 t TRX_OFF → TR6 7 t RX_ON → TR7 8 t PLL_ON → TR8 9 t RX_ON → TR9 10 t PLL_ON → TR10 11 t BUSY_TX → TR11 12 t ...
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AT86RF230 28 Bit 3 0x01 R Read/Write Reset value 0 • Bit 7 – CCA_DONE Refer to section 8.6. • Bit 6 – CCA_STATUS Refer to section 8.6. • Bit 5 – Reserved • Bit [4:0] – TRX_STATUS The register ...
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Extended Operating Mode 5131E-MCU Wireless-02/09 Bit 7 0x02 TRAC_STATUS Read/Write R Reset value 0 Bit 3 0x02 Read/Write R/W R/W Reset value 0 • Bit [7:5] – TRAC_STATUS Refer to section 7.2.6. • Bit [4:0] – TRX_CMD A write ...
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AT86RF230 30 The RX_AACK transaction consists of: • Frame reception • Address filtering and automatic FCS check • Interrupt indicating frame reception passes address filtering and FCS check • Automatic ACK frame transmission, if necessary For details on ...
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Figure 7-5. Extended Operating Mode State Diagram P_ON (Power-on after VDD) XOSC=ON Pull=ON FORCE_TRX_OFF (all states except SLEEP) SFD BUSY_RX Detected RX_ON (Receive State) (Rx Listen State) Frame End RX_ON_NOCLK From (Rx Listen State) TRX_OFF CLKM=OFF SFD Detected BUSY_RX_AACK RX_AACK_ON ...
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Configuration AT86RF230 32 RX_AACK: The state RX_AACK_ON is entered by writing the command RX_AACK_ON to the register bits TRX_CMD in register 0x02 (TRX_STATE). The state change shall be confirmed by reading register 0x01 (TRX_STATUS) that changes to RX_AACK_ON or ...
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Extended Operating Mode Description 7.2.3.1 RX_AACK_ON – Receive with Automatic ACK 5131E-MCU Wireless-02/09 In the RX_AACK_ON state, the radio transceiver listens for incoming frames. After detecting a frame start (SFD), the radio transceiver state changes to BUSY_RX_AACK (register 0x01) ...
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Figure 7-7. Example Timing of an RX_AACK Transaction 0 64 Frame Type TRX_STATE RX_AACK_ON RX/TX IRQ Typ. Processing Delay AT86RF230 34 Figure 7-6. Flow Diagram of RX_AACK 512 Data Frame (Length = 10, ACK=1) SFD BUSY_RX_AACK RX TRX_END μ 16 ...
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TX_ARET_ON – Transmit with Automatic CSMA-CA Retry 5131E-MCU Wireless-02/09 The implemented TX_ARET algorithm is shown in Figure 7-8. The TX_ARET transaction is started by either a rising edge on SLP_TR pin or by writing a TX_START command to register ...
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AT86RF230 36 Figure 7-8 Flow Diagram of TX_ARET Figure 7-9 shows a TX_ARET transaction with the related timing. In this example a data frame of length 10 with ACK request is transmitted. Furthermore the following constrains are assumed: • Register ...
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Figure 7-9 Timing Example of a TX_ARET Transaction 0 FrameType TRX_STATE TX_ARET_ON RX/TX SLP_TR IRQ μ Typ. Processing Delay 128 s Register settings: 0x2C: MAX_FRAME_RETRIES=0 0x2C: MAX_CSMA_RRTRIES=0 0x2E: MIN_BE=0 7.2.3.3 RX_AACK_ON_NOCLK – RX_AACK_ON without CLKM 7.2.4 Interrupt Handling in Extended ...
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Register Summary Table 7-6. Register Summary Reg.-Address Register Name 0x01 TRX_STATUS 0x02 TRX_STATE 0x20 - 0x2B 0x2C XAH_CTRL 0x2D CSMA_SEED_0 0x2E CSMA_SEED_1 7.2.6 Register Description – Control Registers AT86RF230 38 Table 7-5. Interrupt Description for Extended Operating Mode IRQ ...
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Wireless-02/09 • Bit 6 – CCA_STATUS Refer to section 8.6. • Bit 5 – Reserved • Bit [4:0] – TRX_STATUS The register bits TRX_STATUS signal the current radio transceiver status. If the requested state transition is not completed yet, ...
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AT86RF230 40 • Bit [7:5] – TRAC_STATUS The status of the TX_ARET algorithm is indicated by register bits TRAC_STATUS. Details of the algorithm and a description of the status information are given in section 7.2.3.2. Table 7-8. State Control Register, ...
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Wireless-02/09 • Bit [7:4] – MAX_FRAME_RETRIES MAX_FRAME_RETRIES specifies the maximum number of frame retransmission in TX_ARET transaction. • Bit [3:1] – MAX_CSMA_RETRIES MAX_CSMA_RETRIES specifies the maximum number of retries in TX_ARET transaction to repeat the random back-off/CCA procedure before ...
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Register Description – Address Registers AT86RF230 42 acknowledgment frame is set in response to a MAC command data request frame, otherwise not. The register bit has to be set before finishing the SHR transmission of the acknowledgment frame. This ...
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Wireless-02/09 Register 0x24 (IEEE_ADDR_0) This register contains bits [7:0] of the 64 bit IEEE address for address filtering. Bit 0x24 Read/Write R/W R/W R/W Reset value Register 0x25 (IEEE_ADDR_1) This register contains bits ...
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AT86RF230 44 Register 0x2A (IEEE_ADDR_6) This register contains bits [55:48] of the 64 bit IEEE address for address filtering. Bit 0x2A Read/Write R/W R/W R/W Reset value Register 0x2B (IEEE_ADDR_7) This register contains bits ...
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Functional Description 8.1 Introduction - Frame Format Figure 8-1 IEEE 802.15.4-2003 Frame Format – PHY Layer Frame Structure Figure 8-2 IEEE 802.15.4-2003 Frame Format – MAC Layer Frame Structure 8.1.1 PHY Protocol Layer Data Unit (PPDU) 8.1.1.1 Synchronization Header ...
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PHY Header (PHR) 8.1.1.3 PHY Payload (PHY Service Data Unit, PSDU) 8.1.2 MAC Protocol Layer Data Unit (MPDU) 8.1.2.1 MAC Header (MHR) Fields 8.1.2.2 Frame Control Field (FCF) AT86RF230 46 The PHY header consists of a single octet following ...
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Sequence number 8.1.2.4 Addressing fields 8.1.2.5 MAC Service Data Unit (MSDU) 5131E-MCU Wireless-02/09 nonbeacon-enabled networks). The AT86RF230 parses this bit during RX_AACK operation and transmits an acknowledgment frame if necessary. Bit 6 the “Intra-PAN” subfield indicates that in a ...
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MAC Footer (MFR) Fields 8.2 Frame Check Sequence (FCS) 8.2.1.1 Overview 8.2.2 CRC calculation AT86RF230 48 The MAC footer consists of a two-octet frame checksum (FCS). The AT86RF230 can generate and evaluate this FCS automatically, for details refer to ...
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Automatic FCS generation 8.2.4 Automatic FCS check 8.2.5 Register Description 5131E-MCU Wireless-02/09 The AT86RF230 automatic FCS generation and insertion is enabled by setting register bit TX_AUTO_CRC_ON to 1. For a frame with a frame length field (PHR) specified as ...
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Energy Detection (ED) 8.3.1 Overview 8.3.2 Request an ED Measurement AT86RF230 50 Register 0x06 (PHY_RSSI) The PHY_RSSI register is a multi purpose register to indicate the current received signal strength (RSSI) and the FCS validity of a received frame. ...
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Data Interpretation 8.3.4 Register Description 8.4 Received Signal Strength Indicator (RSSI) 5131E-MCU Wireless-02/09 The measurement result is stored to register 0x07 (PHY_ED_LEVEL) 140 µs after its initialization. The value is always 0 if the AT86RF230 is not in any ...
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Overview 8.4.2 Reading RSSI 8.4.3 Data Interpretation 8.4.4 Register Description AT86RF230 52 The RSSI is a 5-bit value indicating the receive power in the selected channel, in steps of 3 dB. No attempt is made to distinguish between IEEE ...
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Link Quality Indication (LQI) 8.5.1 Overview 8.5.2 Request an LQI Measurement 5131E-MCU Wireless-02/09 The IEEE 802.15.4 standard defines the LQI measurement as a characterization of the strength and/or quality of a received packet. The use of the LQI result ...
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Data Interpretation 8.6 Clear Channel Assessment (CCA) 8.6.1 Overview AT86RF230 54 information can be read as an extra byte from the Frame Buffer (see section 9.1). The LQI byte can be uploaded after the TRX_END interrupt. A low LQI ...
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CCA Configuration and Request 8.6.3 Data Interpretation 8.6.4 Register Description 5131E-MCU Wireless-02/09 The CCA modes are configurable via register 0x08 (PHY_CC_CCA). The 4 bit value CCA_ED_THRES of register 0x09 (CCA_THRES) defines the received power threshold of the “energy above ...
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AT86RF230 56 Table 8-5. Status CCA Algorithm Register Bit Value CCA_DONE 0 1 • Bit 6 – CCA_STATUS CCA_STATUS register bit indicates the result of a CCA request. Each read access to register 0x01 resets the CCA_STATUS bit. Table 8-6. ...
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Wireless-02/09 Register 0x09 (CCA_THRES) This register contains the threshold level for CCA-ED measurement. Bit 7 0x09 Read/Write R/W R/W Reset value 1 Bit 3 0x09 R/W R/W Read/Write Reset value 0 • Bit [7:4] – Reserved • Bit [3:0] ...
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Module Description 9.1 Receiver (RX) 9.1.1 Overview 9.1.2 Configuration 9.2 Transmitter (TX) 9.2.1 Overview AT86RF230 58 The AT86RF230 receiver is spitted into an analog radio front end and a digital base band processor (RX BBP), see Figure 3-1. The ...
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Configuration 9.2.3 Register Description 5131E-MCU Wireless-02/09 connected to bidirectional differential antenna pins (RFP, RFN), so that no external antenna switch is needed. In Basic Operating Mode a transmission is started from PLL_ON state by either writing TX_START to register ...
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Frame Buffer 9.3.1 Frame Buffer Data Management 9.3.2 User accessible Frame Content AT86RF230 60 Register Bits Value [3:0] 0xB 0xC 0xD 0xE 0xF The AT86RF230 contains a 128 byte dual port SRAM. One port is connected to the SPI ...
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Figure 9-1. Frame Structure 9.3.3 Frame Buffer Interrupt Handling 5131E-MCU Wireless-02/09 A frame comprises two sections, the fixed internally generated SHR field and the user accessible part stored in the Frame Buffer. The first fixed part of the frame consists ...
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Voltage Regulators (AVREG, DVREG) 9.4.1 Overview AT86RF230 62 the SPI transfer rate shall be lower than 250 Kbit/s to ensure no TRX_UR interrupt occurs. Note, during the Frame Buffer read access the TRX_UR interrupt is first valid 64 µs ...
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Configure the Voltage Regulators 9.4.3 Data Interpretation 9.4.4 Register Description 5131E-MCU Wireless-02/09 The voltage regulators can be configured by the register 0x10 (VREG_CTRL recommended to use the internal regulators, but it is also possible to supply the ...
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Battery Monitor (BATMON) 9.5.1 Overview AT86RF230 64 • Bit [5:4] – Reserved • Bit 7 – DVREG_EXT The register bit DVREG_EXT defines whether the internal digital voltage regulator or an external regulator is used to supply the digital low ...
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Data Interpretation 9.5.3 BATMON Interrupt Handling 9.5.4 Register Description 5131E-MCU Wireless-02/09 The signal bit BATMON_OK of register 0x11 (BATMON) indicates the current value of the battery voltage: • If BATMON_OK = 0, the battery voltage is lower than the ...
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Crystal Oscillator (XOSC) AT86RF230 66 Table 9-6. Battery Monitor Status Register Bit Value BATMON_OK 0 1 • Bit 4 – BATMON_HR The register bit BATMON_HR selects the range and resolution of the battery monitor. Table 9-7. Battery Monitor Voltage ...
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Overview 9.6.2 Integrated Oscillator Setup 5131E-MCU Wireless-02/09 The crystal oscillator generates the reference frequency for the AT86RF230. All other internally generated frequencies of the radio transceiver are derived from this unique frequency. Therefore, the overall system performance is mainly ...
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External Reference Frequency Setup 9.6.4 Master Clock Signal Output (CLKM) AT86RF230 68 Figure 9-4. Simplified XOSC Schematic with External Components EVDD XTAL_TRIM[3:0] C TRIM XTAL2 CX C PAR When using an external reference frequency, the signal needs to be ...
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Register Description 5131E-MCU Wireless-02/09 To reduce power consumption and spurious emissions recommended to turn off the CLKM clock when not in use or to reduce its driver strength to a minimum, refer to section 4.3. Note: During ...
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AT86RF230 70 Register Bit Value 1 • Bit [2:0] – CLKM_CTRL The register bits CLKM_CTRL set clock rate of pin CLKM. Table 9-11. Clock Rate at Pin CLKM Register Bit Value CLKM_CTRL ...
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Frequency Synthesizer (PLL) 9.7.1 Overview 9.7.2 RF Channel Selection 9.7.3 Calibration Loops 5131E-MCU Wireless-02/09 Register Bit Value 0x1 … 0xF The main PLL features are: • Generate RX/TX frequencies for all IEEE 802.15.4 - 2.4 GHz channels • Fully ...
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PLL Interrupt Handling 9.7.5 Register Description AT86RF230 72 (PLL_DCU). To start the calibrations routines the device should be in state PLL_ON. The center frequency tuning takes a maximum of 80 µs. The completion is indicated by a PLL_LOCK interrupt. ...
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Wireless-02/09 Register Bit Value 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A Register 0x1A (PLL_CF) The register PLL_CF controls the operation of the center frequency calibration loop. Bit 7 0x1A PLL_CF_START Read/Write R/W R/W Reset ...
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Automatic Filter Tuning (FTN) AT86RF230 74 • Bit 7 – PLL_DCU_START PLL_DCU_START = 1 initiates the delay cell calibration. The calibration cycle has finished after maximum of 6 µs. The register bit is cleared immediately after the register write ...
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Radio Transceiver Usage 10.1 Frame Receive Procedure 10.2 Frame Transmit Procedure 5131E-MCU Wireless-02/09 This section describes basic procedures to receive and transmit frames using the AT86RF230. For a detailed programming description refer to application note AVR2009 “AT86RF230 – Software ...
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AT86RF230 76 Figure 9-7. Frame Transmit Procedure - Transactions between AT86RF230 and Microcontroller Alternatively, the frame transmission can be started before the frame data download as described in Figure 9-8. This is useful for time critical applications. At the rising ...
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Technical Parameters 11.1 Absolute Maximum Ratings Table 11-1. Absolute Maximum Ratings No Parameter 11.1.1 Storage temperature 11.1.2 Lead temperature 11.1.3 ESD robustness 11.1.4 Input RF level Voltage on all pins (except pins 11.1 13, 14, 29) 11.1.6 ...
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Digital Interface Timing Specifications Table 11-4. Digital Interface Timing Parameters No Parameter 11.4.1 SCLK frequency (synchronous mode) 11.4.2 SCLK frequency (asynchronous mode) 11.4.3 SEL low to MISO active 11.4.4 SCLK to MISO out 11.4.5 MOSI setup time 11.4.6 MOSI ...
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Transmitter Specifications Table 11-6. TX Parameters No Parameter 11.6.1 Output power 11.6.2 Output power range 11.6.3 Output power tolerance 11.6.4 TX Return loss 11.6.5 EVM 11.6.6 Harmonics 2nd harmonic 3rd harmonic 11.6.7 Spurious emissions 30 – ≤ 1000 MHz ...
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No Parameter 11.7.10 TX/RX carrier frequency offset tolerance 11.7.11 3rd-order intercept point 11.7.12 2nd-order intercept point 11.7.13 RSSI tolerance 11.7.14 RSSI dynamic range 11.7.15 RSSI resolution 11.7.16 RSSI sensitivity 11.7.17 Minimum RSSI value 11.7.18 Maximum RSSI value 11.8 Current Consumption ...
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Register Reference Table 12-1. Register Summary – Non Reserved Registers Addr. Name Bit 7 0x01 TRX_STATUS CCA_DONE CCA_STATUS 0x02 TRX_STATE TRAC_STATUS 0x03 TRX_CTRL_0 PAD_IO 0x05 PHY_TX_PWR TX_AUTO_CRC_ON 0x06 PHY_RSSI RX_CRC_VALID 0x07 PHY_ED_LEVEL 0x08 PHY_CC_CCA CCA_REQUEST 0x09 CCA_THRES 0x0E IRQ_MASK ...
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Table 12-2. Register Summary – Reset values Address Reset Value 0x00 0x00 0x01 0x00 0x02 0x00 0x03 0x19 0x04 0x00 0x05 0x00 0x06 0x00 0x07 0x00 0x08 0x2B 0x09 0xC7 0x0A 0xBC 0x0B 0xA7 0x0C 0x04 0x0D 0x00 0x0E 0xFF ...
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Abbreviations 5131E-MCU Wireless-02/09 AACK — Auto acknowledge ACK — Acknowledge ADC — Analog-to-digital converter AGC — Automatic gain control ARET — Auto retry AVREG — Analog voltage regulator AWGN — Additive White Gaussian Noise BATMON — Battery monitor BBP — ...
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AT86RF230 84 PAN — Personal area network PCB — Printed circuit board PER — Packet error rate PHY — Physical layer PHR — PHY Header PLL — Phase-locked loop POR — Power-on reset PPF — Poly-phase filter PRBS — Pseudo ...
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... Wireless-02/09 Voltage Range Temperature Range 1.8V – 3.6V Industrial (-40° +85° C) Lead-free/Halogen-free T&R quantity 5,000. Note: Please contact your local Atmel sales office for more detailed ordering information and minimum quantities. Recommended soldering profile is specified in IPC/JEDEC J-STD-.020C. Velocity [m/ 2.5 ...
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... Dimension b applies to metallized terminal and is measured between 0.15 mm and 0.30 mm from the terminal tip. If the terminal has the optional radius on the other end of the terminal, the dimension should not be measured in that radius area. Package Drawing Contact: packagedrawings@atmel.com AT86RF230 86 D ...
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Appendix A - Continuous Transmission Test Mode A.1 - Overview A.2 - Configuration 5131E-MCU Wireless-02/09 The Continuous Transmission Test Mode offers the following features: • Continuous frame transmission • Continuous wave signal transmission The AT86RF230 offers a Continuous Transmission Test ...
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... RFP|RFN) Reset TST for Normal Operation 16 (TST = L) RESET 17 The functionality of the Continuous Transmit Mode is not characterized by Atmel and therefore not guaranteed. The normal operation of the AT86RF230 is only guaranteed if pin TST is always logic low. Write 0x01 to register 0x0E Write 0x03 to register 0x02 ...
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Appendix B - Errata AT86RF230 Rev. B AT86RF230 Rev. A 5131E-MCU Wireless-02/09 No known errata. 1. Data frames with destination address=0xFFFF is acknowledged in RX_AACK According to IEEE 802.15.4-2003 data frames with destination address=0xFFFF (broadcast) should not have the acknowledgment ...
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AT86RF230 90 set TRX_CMD = RX_ON o wait for TRX_END IRQ o read TRAC_STATUS o set TRX_CMD = TX_ARET_ON o poll for TRX_STATUS == TX_ARET_ON o Switching to RX_ON is not executed during BUSY_TX_ARET but immediately after BUSY_TX_ARET has completed. ...
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References 5131E-MCU Wireless-02/09 [1] IEEE Std 802.15.4-2003: Wireless Medium Access Control (MAC) and Physical Layer (PHY) Specifications for Low-Rate Wireless Personal Area Networks (LR-WPANs) [2] ANSI / ESD-STM5.1-2001: ESD Association Standard Test Method for electrostatic discharge sensitivity testing – Human ...
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... Minor editorial changes The AT86RF230 data sheet was fully revised and modifications of silicon revision AT86RF230 Rev. B were incorporated. A migration note of silicon revision A to revision B is available on www.atmel.com. The most important modifications are: 4. Device version number in register 0x1D (VERSION_NUM) changed to 2 (section 6.3) 5 ...
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Table of Contents 5131E-MCU Wireless-02/09 1 Pin-out Diagram ..................................................................................2 Disclaimer...............................................................................................2 2 Overview ..............................................................................................2 3 General Circuit Description................................................................3 4 Pin Description....................................................................................4 4.1 Supply and Ground Pins ........................................................................................ 4 4.2 Analog and RF Pins ............................................................................................... 5 4.3 Digital Pins.............................................................................................................. 6 4.3.1 Driver ...
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AT86RF230 94 8.1.2 MAC Protocol Layer Data Unit (MPDU)....................................................................... 46 8.2 Frame Check Sequence (FCS) ............................................................................ 48 8.2.2 CRC calculation........................................................................................................... 48 8.2.3 Automatic FCS generation .......................................................................................... 49 8.2.4 Automatic FCS check .................................................................................................. 49 8.2.5 Register Description .................................................................................................... 49 8.3 Energy ...
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Wireless-02/09 9.6.1 Overview ..................................................................................................................... 67 9.6.2 Integrated Oscillator Setup .......................................................................................... 67 9.6.3 External Reference Frequency Setup.......................................................................... 68 9.6.4 Master Clock Signal Output (CLKM)............................................................................ 68 9.6.5 Register Description .................................................................................................... 69 9.7 Frequency Synthesizer (PLL)............................................................................... 71 9.7.1 Overview ..................................................................................................................... 71 9.7.2 ...
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AT86RF230 96 Data Sheet Revision History ...............................................................92 Rev. 5131D-ZIGB-12/03/07........................................................................................ 92 Rev. 5131C-ZIGB-05/22/07........................................................................................ 92 Rev. 5131A-ZIGB-06/14/06........................................................................................ 92 Table of Contents.................................................................................93 5131E-MCU Wireless-02/09 ...
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Wireless-02/09 AT86RF230 97 ...
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... BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’ ...