ATMEGA64RZAV-10PU Atmel, ATMEGA64RZAV-10PU Datasheet - Page 169

• Manufacturer Part Number: ATMEGA64RZAV-10PU
• Description: MCU ATMEGA644/AT86RF230 40-DIP
• Manufacturer: Atmel
• Series: ATMEGAr

Specifications of ATMEGA64RZAV-10PU

• Frequency: 2.4GHz
• Modulation Or Protocol: 802.15.4 Zigbee
• Power - Output: 3dBm
• Sensitivity: -101dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Data Interface: PCB, Surface Mount
• Memory Size: 64kB Flash, 2kB EEPROM, 4kB RAM
• Antenna Connector: PCB, Surface Mount
• Package / Case: 40-DIP (0.600", 15.24mm)
• Wireless Frequency: 2.4 GHz
• Interface Type: JTAG, SPI
• Output Power: 3 dBm
• For Use With: ATSTK600-TQFP32 - STK600 SOCKET/ADAPTER 32-TQFPATAVRISP2 - PROGRAMMER AVR IN SYSTEMATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Applications: -
• Data Rate - Maximum: -
• Current - Transmitting: -
• Current - Receiving: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: ATmega64

17.4.1
2593N–AVR–07/10
Parity Bit Calculation
be directly followed by a new frame, or the communication line can be set to an idle (high) state.
Figure 17-4
optional.
Figure 17-4. Frame Formats
must be
The frame format used by the USART is set by the UCSZn2:0, UPMn1:0 and USBSn bits in
UCSRnB and UCSRnC. The Receiver and Transmitter use the same setting. Note that changing
the setting of any of these bits will corrupt all ongoing communication for both the Receiver and
Transmitter.
The USART Character SiZe (UCSZn2:0) bits select the number of data bits in the frame. The
USART Parity mode (UPMn1:0) bits enable and set the type of parity bit. The selection between
one or two stop bits is done by the USART Stop Bit Select (USBSn) bit. The Receiver ignores
the second stop bit. An FE (Frame Error) will therefore only be detected in the cases where the
first stop bit is zero.
The parity bit is calculated by doing an exclusive-or of all the data bits. If odd parity is used, the
result of the exclusive or is inverted. The relation between the parity bit and data bits is as
follows::
If used, the parity bit is located between the last data bit and first stop bit of a serial frame.
St
(n)
P
Sp
IDLE
P
P
d
even
odd
n
illustrates the possible combinations of the frame formats. Bits inside brackets are
(IDLE)
St
Start bit, always low.
Data bits (0 to 8).
Parity bit. Can be odd or even.
Stop bit, always high.
No transfers on the communication line (RxDn or TxDn). An IDLE line
high.
Parity bit using even parity
Parity bit using odd parity
Data bit n of the character
P
0
P
even
odd
1
=
=
d
d
2
n 1
n 1
–
–
3
⊕
⊕
…
…
4
⊕
⊕
FRAME
[5]
d
d
3
3
⊕
⊕
[6]
d
d
2
2
⊕
⊕
[7]
d
d
1
1
[8]
⊕
⊕
d
d
0
0
[P]
⊕
⊕
0
1
Sp1 [Sp2]
ATmega644
(St / IDLE)
169