ATMEGA64RZAV-10PU Atmel, ATMEGA64RZAV-10PU Datasheet - Page 14

• Manufacturer Part Number: ATMEGA64RZAV-10PU
• Description: MCU ATMEGA644/AT86RF230 40-DIP
• Manufacturer: Atmel
• Series: ATMEGAr

Specifications of ATMEGA64RZAV-10PU

• Frequency: 2.4GHz
• Modulation Or Protocol: 802.15.4 Zigbee
• Power - Output: 3dBm
• Sensitivity: -101dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Data Interface: PCB, Surface Mount
• Memory Size: 64kB Flash, 2kB EEPROM, 4kB RAM
• Antenna Connector: PCB, Surface Mount
• Package / Case: 40-DIP (0.600", 15.24mm)
• Wireless Frequency: 2.4 GHz
• Interface Type: JTAG, SPI
• Output Power: 3 dBm
• For Use With: ATSTK600-TQFP32 - STK600 SOCKET/ADAPTER 32-TQFPATAVRISP2 - PROGRAMMER AVR IN SYSTEMATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Applications: -
• Data Rate - Maximum: -
• Current - Transmitting: -
• Current - Receiving: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: ATmega64

5.7
5.8
14
Instruction Execution Timing
Reset and Interrupt Handling
ATmega644
This section describes the general access timing concepts for instruction execution. The AVR
CPU is driven by the CPU clock clk
chip. No internal clock division is used.
Figure 5-4
vard architecture and the fast-access Register File concept. This is the basic pipelining concept
to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost,
functions per clocks, and functions per power-unit.
Figure 5-4.
Figure 5-5 on page 14
cycle an ALU operation using two register operands is executed, and the result is stored back to
the destination register.
Figure 5-5.
The AVR provides several different interrupt sources. These interrupts and the separate Reset
Vector each have a separate program vector in the program memory space. All interrupts are
assigned individual enable bits which must be written logic one together with the Global Interrupt
Enable bit in the Status Register in order to enable the interrupt. Depending on the Program
Counter value, interrupts may be automatically disabled when Boot Lock bits BLB02 or BLB12
are programmed. This feature improves software security. See the section
ming” on page 284
The lowest addresses in the program memory space are by default defined as the Reset and
Interrupt Vectors. The complete list of vectors is shown in
determines the priority levels of the different interrupts. The lower the address the higher is the
Register Operands Fetch
2nd Instruction Execute
3rd Instruction Execute
1st Instruction Execute
ALU Operation Execute
2nd Instruction Fetch
3rd Instruction Fetch
4th Instruction Fetch
1st Instruction Fetch
Total Execution Time
shows the parallel instruction fetches and instruction executions enabled by the Har-
Result Write Back
The Parallel Instruction Fetches and Instruction Executions
Single Cycle ALU Operation
for details.
clk
clk
CPU
CPU
shows the internal timing concept for the Register File. In a single clock
CPU
T1
T1
, directly generated from the selected clock source for the
T2
T2
”Interrupts” on page
T3
T3
”Memory Program-
55. The list also
2593N–AVR–07/10
T4
T4