SAK-TC1796-256F150E BD Infineon Technologies, SAK-TC1796-256F150E BD Datasheet - Page 86

• Manufacturer Part Number: SAK-TC1796-256F150E BD
• Description: IC MCU 32BIT FLASH PG-BGA-416
• Manufacturer: Infineon Technologies
• Series: TC17xxr

Specifications of SAK-TC1796-256F150E BD

• Core Processor: TriCore
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: ASC, CAN, EBI/EMI, MLI, MSC, SSC
• Peripherals: DMA, POR, WDT
• Number Of I /o: 123
• Program Memory Size: 2MB (2M x 8)
• Program Memory Type: FLASH
• Ram Size: 256K x 8
• Voltage - Supply (vcc/vdd): 1.42 V ~ 1.58 V
• Data Converters: A/D 44x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 416-BGA
• Packages: PG-BGA-416
• Max Clock Frequency: 150.0 MHz
• Sram (incl. Cache): 256.0 KByte
• Can Nodes: 4
• A / D Input Lines (incl. Fadc): 44
• Program Memory: 2.0 MB
• For Use With: B158-H8537-G2-X-7600IN - KIT STARTER TC179X FAMILY
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: KT1796256F150EBDXP; SAK-TC1796-256F150EBDIN; SP000228336

Table 12
Parameter
Absolute sum of short
circuit currents of the
device
External load
capacitance
1) Digital supply voltages applied to the TC1796 must be static regulated voltages which allow a typical voltage
2)
3) Voltage overshoot up to 1.7 V is permissible at Power-Up and PORST low, provided the pulse duration is less
4) Voltage overshoot to 4 V is permissible at Power-Up and PORST low, provided the pulse duration is less than
5) The
6) This applies only during power down state. During normal SRAM operation regular
7) The TC1796 uses a static design, so the minimum operation frequency is 0 MHz. Due to test time restriction
8) The PLL jitter characteristics add to this value according to the application settings. See the PLL jitter
9) Applicable for digital outputs.
10) See additional document “TC1796 Pin Reliability in Overload“ for overload current definitions.
Table 13
Group
1
2
3
4
5
6
7
8
Data Sheet
swing of ±5%.
V
in future steps and products is kept open.
than 100 µs and the cumulated summary of the pulses does not exceed 1 h.
100 µs and the cumulated summary of the pulses does not exceed 1 h
of a stand-by operation, the core voltage must not float, but must be pulled low, in order to avoid internal cross-
currents.
no lower frequency boundary is tested, however.
parameters.
DDOSC
V
DDSB
and
Pins
P4.[7:0]
P4.[14:8]
P4.15, SLSO[1:0], SCLK0, MTSR0, MRST0, SLSI0
WAIT, HOLD, BC[3:0], HLDA, MR/W, BAA, CSCOMB
CS[3:0], RD, RD/WR, BREQ, ADV, BFCLKO
BFCLKI, D[31:24]
D[23:16]
D[15:8]
must be properly connected and supplied with power. If not, the TC1796 will not operate. In case
V
SSOSC
Operating Condition Parameters
Pin Groups for Overload/Short-Circuit Current Sum Parameter
are not bonded externally in the BC and BD steps of TC1796. An option for bonding them
Symbol
Σ|
C
L
I
SC
|
SR
SR –
Min.
–
86
Values
Typ. Max.
–
–
100
–
Unit Note /
mA
pF
Electrical Parameters
V
Test Condition
See note
Depending on pin
class. See DC
characteristics
DD
has to be applied.
V1.0, 2008-04
10)
TC1796