SAK-TC1796-256F150E BD Infineon Technologies, SAK-TC1796-256F150E BD Datasheet - Page 112

• Manufacturer Part Number: SAK-TC1796-256F150E BD
• Description: IC MCU 32BIT FLASH PG-BGA-416
• Manufacturer: Infineon Technologies
• Series: TC17xxr

Specifications of SAK-TC1796-256F150E BD

• Core Processor: TriCore
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: ASC, CAN, EBI/EMI, MLI, MSC, SSC
• Peripherals: DMA, POR, WDT
• Number Of I /o: 123
• Program Memory Size: 2MB (2M x 8)
• Program Memory Type: FLASH
• Ram Size: 256K x 8
• Voltage - Supply (vcc/vdd): 1.42 V ~ 1.58 V
• Data Converters: A/D 44x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 416-BGA
• Packages: PG-BGA-416
• Max Clock Frequency: 150.0 MHz
• Sram (incl. Cache): 256.0 KByte
• Can Nodes: 4
• A / D Input Lines (incl. Fadc): 44
• Program Memory: 2.0 MB
• For Use With: B158-H8537-G2-X-7600IN - KIT STARTER TC179X FAMILY
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: KT1796256F150EBDXP; SAK-TC1796-256F150EBDIN; SP000228336

4.3.5
Note: All PLL characteristics defined on this and the next page are verified by design
Table 24
Parameter
Accumulated jitter
VCO frequency range
PLL base frequency
PLL lock-in time
1) The CPU base frequency which is selected after reset is calculated by dividing the limit values by 16 (this is
Phase Locked Loop Operation
When PLL operation is enabled and configured, the PLL clock
clock
and
clock outputs BFCLKO, TRCLK, and SYSCLK (P1.12) which are derived from the PLL
clock
There will be defined two formulas that define the (absolute) approximate maximum
value of jitter
and the number
Data Sheet
the K factor after reset).
f
SYS
f
f
characterization.
VCO
CPU
is defined by:
) is constantly adjusted to the selected frequency. The relation between
.
Phase Locked Loop (PLL)
D
PLL Parameters (Operating Conditions apply)
P
P
P
P
×
×
in ns dependent on the K-factor, the CPU clock frequency
K
K
of consecutive
1)
<
≥
385
385
f
VCO
= K ×
Symbol
D
f
f
t
VCO
PLLBASE
L
P
D
D
p ns
p ns
f
f
CPU
[
[
CPU
]
]
. The PLL causes a jitter of
clock periods.
=
=
Min.
See
Figure 3
2
400
600
500
140
150
200
–
112
-------------------------------------------- -
f
------------------------------------------ -
f
cpu
cpu
7000
2
2
2700000
[
[
MHz
MHz
Values
×
Typ.
–
–
–
–
–
–
–
–
P
]
]
×
×
K
K
2
+
Max.
–
500
700
600
320
400
480
200
+
0 535
0 535
,
f
,
VCO
Electrical Parameters
(and with it the CPU
f
CPU
Unit Note /
–
MHz –
MHz –
MHz –
MHz –
MHz –
MHz –
µs
and affects the
V1.0, 2008-04
f
CPU
Test Con
dition
–
–
TC1796
in MHz,
f
VCO
(1)
(2)