SAK-TC1796-256F150E BD Infineon Technologies, SAK-TC1796-256F150E BD Datasheet - Page 67

• Manufacturer Part Number: SAK-TC1796-256F150E BD
• Description: IC MCU 32BIT FLASH PG-BGA-416
• Manufacturer: Infineon Technologies
• Series: TC17xxr

Specifications of SAK-TC1796-256F150E BD

• Core Processor: TriCore
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: ASC, CAN, EBI/EMI, MLI, MSC, SSC
• Peripherals: DMA, POR, WDT
• Number Of I /o: 123
• Program Memory Size: 2MB (2M x 8)
• Program Memory Type: FLASH
• Ram Size: 256K x 8
• Voltage - Supply (vcc/vdd): 1.42 V ~ 1.58 V
• Data Converters: A/D 44x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 416-BGA
• Packages: PG-BGA-416
• Max Clock Frequency: 150.0 MHz
• Sram (incl. Cache): 256.0 KByte
• Can Nodes: 4
• A / D Input Lines (incl. Fadc): 44
• Program Memory: 2.0 MB
• For Use With: B158-H8537-G2-X-7600IN - KIT STARTER TC179X FAMILY
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: KT1796256F150EBDXP; SAK-TC1796-256F150EBDIN; SP000228336

3.17
The TC1796’s STM is designed for global system timing applications requiring both high
precision and long range.
Features
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The STM is an upward counter, running either at the system clock frequency
fraction of it. In case of a power-on reset, a watchdog reset, or a software reset, the STM
is reset. After one of these reset conditions, the STM is enabled and immediately starts
counting up. It is not possible to affect the contents of the timer during normal operation
of the TC1796. The timer registers can only be read but not written to. The STM can be
optionally disabled or suspended for power-saving and debugging purposes via its clock
control register. In suspend mode of the TC1796, the STM clock is stopped but all
registers are still readable.
The System Timer can be read in sections from seven registers, STM_TIM0 through
STM_TIM6, which select increasingly higher-order 32-bit ranges of the System Timer.
These can be viewed as individual 32-bit timers, each with a different resolution and
timing range. For getting a synchronous and consistent reading of the complete STM
contents, a capture register (STM_CAP), is implemented. It latches the contents of the
high part of the STM each time when one of the registers STM_TIM0 to STM_TIM5 is
read. Thus, it holds the upper value of the timer at exactly the same time when the lower
part is read. The second read operation would then read the contents of the STM_CAP
to get the complete timer value.
The content of the 56-bit System Timer can be compared against the content of two
compare values stored in the compare registers. Interrupts can be generated on a
compare match of the STM with the STM_CMP0 or STM_CMP1 registers.
The maximum clock period is 2
30.47 years before overflowing. Thus, it is capable of continuously timing the entire
expected product life-time of a system without overflowing.
Data Sheet
Free-running 56-bit counter
All 56 bits can be read synchronously
Different 32-bit portions of the 56-bit counter can be read synchronously
Flexible interrupt generation based on compare match with partial STM content
Driven by max. 75 MHz (=
Counting starts automatically after a reset operation
STM is reset by:
– Watchdog reset
– Software reset (RST_REQ.RRSTM must be set)
– Power-on reset
STM is not reset at a hardware reset
STM can be halted in debug/suspend mode
System Timer
f
56
SYS
×
, default after reset =
f
STM
. At
67
f
STM
= 75 MHz, for example, the STM counts
f
SYS
/2)
Functional Description
V1.0, 2008-04
f
SYS
TC1796
or at a