SAK-TC1796-256F150E BD Infineon Technologies, SAK-TC1796-256F150E BD Datasheet - Page 100

• Manufacturer Part Number: SAK-TC1796-256F150E BD
• Description: IC MCU 32BIT FLASH PG-BGA-416
• Manufacturer: Infineon Technologies
• Series: TC17xxr

Specifications of SAK-TC1796-256F150E BD

• Core Processor: TriCore
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: ASC, CAN, EBI/EMI, MLI, MSC, SSC
• Peripherals: DMA, POR, WDT
• Number Of I /o: 123
• Program Memory Size: 2MB (2M x 8)
• Program Memory Type: FLASH
• Ram Size: 256K x 8
• Voltage - Supply (vcc/vdd): 1.42 V ~ 1.58 V
• Data Converters: A/D 44x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 416-BGA
• Packages: PG-BGA-416
• Max Clock Frequency: 150.0 MHz
• Sram (incl. Cache): 256.0 KByte
• Can Nodes: 4
• A / D Input Lines (incl. Fadc): 44
• Program Memory: 2.0 MB
• For Use With: B158-H8537-G2-X-7600IN - KIT STARTER TC179X FAMILY
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: KT1796256F150EBDXP; SAK-TC1796-256F150EBDIN; SP000228336

Table 17
Parameter
Conversion time
Converter Clock
Input resistance of
the analog voltage
path (Rn, Rp)
Channel Amplifier
Cutoff Frequency
Settling Time of a
Channel Amplifier
after changing ENN
or ENP
1) Calibration of the gain is possible for the gain of 1 and 2, and not possible for the gain of 4 and 8.
2) Calibration should be performed at each power-up. In case of continuous operation, calibration should be
3) The offset error voltage drifts over the whole temperature range maximum ±3 LSB.
4) Applies when the gain of the channel equals one. For the other gain settings, the offset error increases; it must
5) Voltage overshoot to 4 V are permissible, provided the pulse duration is less than 100 µs and the cumulated
6) Voltage overshoot to 1.7 V are permissible, provided the pulse duration is less than 100 µs and the cumulated
7) A running conversion may become inexact in case of violating the normal operating conditions (voltage
8) Current peaks of up to 40 mA with a duration of max. 2 ns may occur
9) This value applies in power-down mode.
10) Not subject to production test, verified by design / characterization.
The calibration procedure should run after each power-up, when all power supply
voltages and the reference voltage have stabilized. The offset calibration must run first,
followed by the gain calibration.
Data Sheet
performed minimum once per week.
be multiplied with the applied gain.
summary of the pulses does not exceed 1 h.
sum of the pulses does not exceed 1 h.
overshoots).
FADC Characteristics (Operating Conditions apply) (cont’d)
Symbol
t
f
R
f
t
C
ADC
COFF
SET
FAIN
CC
CC
CC –
CC –
CC –
Min.
100
2
100
Values
Typ. Max.
–
–
–
–
–
21
75
200
–
5
Unit
CLK of
f
MHz
kΩ
MHz
µsec
ADC
Electrical Parameters
Note /
Test Condition
10-bit conversion
–
10)
–
–
V1.0, 2008-04
TC1796