SAK-TC1796-256F150E BD Infineon Technologies, SAK-TC1796-256F150E BD Datasheet - Page 45

• Manufacturer Part Number: SAK-TC1796-256F150E BD
• Description: IC MCU 32BIT FLASH PG-BGA-416
• Manufacturer: Infineon Technologies
• Series: TC17xxr

Specifications of SAK-TC1796-256F150E BD

• Core Processor: TriCore
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: ASC, CAN, EBI/EMI, MLI, MSC, SSC
• Peripherals: DMA, POR, WDT
• Number Of I /o: 123
• Program Memory Size: 2MB (2M x 8)
• Program Memory Type: FLASH
• Ram Size: 256K x 8
• Voltage - Supply (vcc/vdd): 1.42 V ~ 1.58 V
• Data Converters: A/D 44x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 416-BGA
• Packages: PG-BGA-416
• Max Clock Frequency: 150.0 MHz
• Sram (incl. Cache): 256.0 KByte
• Can Nodes: 4
• A / D Input Lines (incl. Fadc): 44
• Program Memory: 2.0 MB
• For Use With: B158-H8537-G2-X-7600IN - KIT STARTER TC179X FAMILY
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: KT1796256F150EBDXP; SAK-TC1796-256F150EBDIN; SP000228336

Features
•
•
•
•
•
•
•
•
•
•
•
Memory Checker
The Memory Checker Module (MEMCHK) makes it possible to check the data
consistency of memories. Any SPB bus master may access the memory checker.
Preferable the DMA controller does it as described hereafter. It uses 8-bit, 16-bit, or 32-
bit DMA moves to read from the selected address area and to write the value read in a
memory checker input register. With each write operation to the memory checker input
register, a polynomial checksum calculation is triggered and the result of the calculation
is stored in the memory checker result register.
The memory checker uses the standard Ethernet polynomial, which is given by:
G
Data Sheet
32
16 independent DMA channels
– 8 DMA channels in each DMA Sub-Block
– Up to 8 selectable request inputs per DMA channel
– 2-level programmable priority of DMA channels within a DMA Sub-Block
– Software and hardware DMA request
– Hardware requests by selected on-chip peripherals and external inputs
Programmable priority of the DMA Sub-Blocks on the bus interfaces
Buffer capability for move actions on the buses (at least 1 move per bus is buffered).
Individually programmable operation modes for each DMA channel
– Single mode: stops and disables DMA channel after a predefined number of DMA
– Continuous mode: DMA channel remains enabled after a predefined number of
– Programmable address modification
Full 32-bit addressing capability of each DMA channel
– 4 GByte address range
– Support of circular buffer addressing mode
Programmable data width of DMA transfer/transaction: 8-bit, 16-bit, or 32-bit
Micro Link bus interface support
Register set for each DMA channel
– Source and destination address register
– Channel control and status register
– Transfer count register
Flexible interrupt generation (the service request node logic for the MLI channels is
also implemented in the DMA module)
All buses connected to the DMA module must work at the same frequency.
Read/write requests of the System Bus Side to the Remote Peripherals are bridged
to the Remote Peripheral Bus (only the DMA is master on the RPB)
= x
transfers
DMA transfers; DMA transaction can be repeated.
32
+ x
26
+ x
23
+ x
22
+ x
16
+ x
12
+ x
11
+ x
10
+ x
45
8
+ x
7
+ x
5
+ x
4
+ x
2
+ x +1
Functional Description
V1.0, 2008-04
TC1796