SAK-TC1796-256F150E BD Infineon Technologies, SAK-TC1796-256F150E BD Datasheet - Page 44

• Manufacturer Part Number: SAK-TC1796-256F150E BD
• Description: IC MCU 32BIT FLASH PG-BGA-416
• Manufacturer: Infineon Technologies
• Series: TC17xxr

Specifications of SAK-TC1796-256F150E BD

• Core Processor: TriCore
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: ASC, CAN, EBI/EMI, MLI, MSC, SSC
• Peripherals: DMA, POR, WDT
• Number Of I /o: 123
• Program Memory Size: 2MB (2M x 8)
• Program Memory Type: FLASH
• Ram Size: 256K x 8
• Voltage - Supply (vcc/vdd): 1.42 V ~ 1.58 V
• Data Converters: A/D 44x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 416-BGA
• Packages: PG-BGA-416
• Max Clock Frequency: 150.0 MHz
• Sram (incl. Cache): 256.0 KByte
• Can Nodes: 4
• A / D Input Lines (incl. Fadc): 44
• Program Memory: 2.0 MB
• For Use With: B158-H8537-G2-X-7600IN - KIT STARTER TC179X FAMILY
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: KT1796256F150EBDXP; SAK-TC1796-256F150EBDIN; SP000228336

3.7
The Direct Memory Access (DMA) Controller of the TC1796 transfers data from data
source locations to data destination locations without intervention of the CPU or other
on-chip devices. One data move operation is controlled by one DMA channel. Sixteen
DMA channels are provided in two independent DMA Sub-Blocks with eight DMA
channels each. The Bus Switch provides the connection of two DMA Sub-Blocks to the
two FPI Bus interfaces and an MLI bus interface. In the TC1796, the FPI Bus interfaces
are connected to System Peripheral Bus and the Remote Peripheral Bus. The third
specific bus interface provides a connection to Micro Link Interface modules (two MLI
modules in the TC1796) and other DMA-related devices (Memory Checker module in the
TC1796).
module.
Figure 6
Data Sheet
Requests of
Decoder
Interrupt
Request
Address
On-chip
Control
Periph.
Nodes
Clock
Units
DMA
Figure 6
DMA Controller and Memory Checker
DMA Controller Block Diagram
SR[15:0]
f
DMA
shows the implementation details and interconnections of the DMA
CH0n_OUT
CH1n_OUT
Arbitration
Arbitration
Selection/
Selection/
Request
Request
DMA Interrupt Control
DMA Sub-Block 0
DMA Sub-Block 1
Control Unitl
DMA Controller
Control Unit
Transaction
Transaction
Channels
Channels
00-07
10-17
DMA
DMA
44
Arbiter/
Control
Switch
Switch
Bus
Functional Description
V1.0, 2008-04
System
Peripheral
Bus
Remote
Peripheral
Bus
Checker
Memory
MCB05680
MLI0
MLI1
TC1796