SAK-TC1796-256F150E BD Infineon Technologies, SAK-TC1796-256F150E BD Datasheet - Page 76

• Manufacturer Part Number: SAK-TC1796-256F150E BD
• Description: IC MCU 32BIT FLASH PG-BGA-416
• Manufacturer: Infineon Technologies
• Series: TC17xxr

Specifications of SAK-TC1796-256F150E BD

• Core Processor: TriCore
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: ASC, CAN, EBI/EMI, MLI, MSC, SSC
• Peripherals: DMA, POR, WDT
• Number Of I /o: 123
• Program Memory Size: 2MB (2M x 8)
• Program Memory Type: FLASH
• Ram Size: 256K x 8
• Voltage - Supply (vcc/vdd): 1.42 V ~ 1.58 V
• Data Converters: A/D 44x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 416-BGA
• Packages: PG-BGA-416
• Max Clock Frequency: 150.0 MHz
• Sram (incl. Cache): 256.0 KByte
• Can Nodes: 4
• A / D Input Lines (incl. Fadc): 44
• Program Memory: 2.0 MB
• For Use With: B158-H8537-G2-X-7600IN - KIT STARTER TC179X FAMILY
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: KT1796256F150EBDXP; SAK-TC1796-256F150EBDIN; SP000228336

3.23
The TC1796 clock system performs the following functions:
•
•
•
•
•
•
The clock system must be operational before the TC1796 is able to run. Therefore, it also
contains special logic to handle power-up and reset operations. Its services are
fundamental to the operation of the entire system, so it contains special fail-safe logic.
Features
•
•
•
•
The TC1796 Clock Generation Unit (CGU) as shown in
clock generation. It basically consists of an main oscillator circuit and a Phase- Locked
Loop (PLL). The PLL can converts a low-frequency external clock signal from the
oscillator circuit to a high-speed internal clock for maximum performance.
The system clock
hardware/software selectable ways:
•
•
•
•
Data Sheet
Acquires and buffers incoming clock signals to create a master clock frequency
Distributes in-phase synchronized clock signals throughout the TC1796’s entire clock
tree
Divides a system master clock frequency into lower frequencies required by the
different modules for operation.
Dynamically reduces power consumption during operation of functional units
Statically reduces power consumption through programmable power-saving modes
Reduces electromagnetic interference (EMI) by switching off unused modules
PLL operation for multiplying clock source by different factors
Direct drive capability for direct clocking
Comfortable state machine for secure switching between basic PLL, direct or
prescaler operation
Sleep and Power-Down Mode support
Direct Drive Mode (PLL Bypass):
In Direct Drive Mode, the PLL is bypassed and the CGU clock outputs are directly fed
from the clock signal
operation of the TC1796 with a reasonably small fundamental mode crystal.
VCO Bypass Mode (Prescaler Mode):
In VCO Bypass Mode,
P-Divider and K-Divider. The system clock
PLL Mode:
In PLL Mode, the PLL is running. The VCO clock
the P factor, multiplied by the PLL (N-Divider). The clock signals
derived from
f
PLL Base Mode:
In PLL Base Mode, the PLL is running at its VCO base frequency and
CPU
/2.
Clock Generation and PLL
f
VCO
f
SYS
by the K-Divider. The system clock
is generated from an oscillator clock
f
f
CPU
OSC
, i.e.
and
f
SYS
f
CPU
are derived from
= f
76
OSC
f
SYS
and
can be equal to
f
VCO
f
SYS
Figure 19
is derived from
f
=
OSC
f
SYS
f
OSC
by the two divider stages,
Functional Description
can be equal to
/2 or
f
OSC
allows a very flexible
f
CPU
f
f
in either of four
OSC
CPU
or
f
OSC
. This allows
f
f
V1.0, 2008-04
and
CPU
CPU
, divided by
TC1796
/2.
and
f
SYS
f
CPU
f
are
SYS
or