SAK-TC1796-256F150E BD Infineon Technologies, SAK-TC1796-256F150E BD Datasheet - Page 42

• Manufacturer Part Number: SAK-TC1796-256F150E BD
• Description: IC MCU 32BIT FLASH PG-BGA-416
• Manufacturer: Infineon Technologies
• Series: TC17xxr

Specifications of SAK-TC1796-256F150E BD

• Core Processor: TriCore
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: ASC, CAN, EBI/EMI, MLI, MSC, SSC
• Peripherals: DMA, POR, WDT
• Number Of I /o: 123
• Program Memory Size: 2MB (2M x 8)
• Program Memory Type: FLASH
• Ram Size: 256K x 8
• Voltage - Supply (vcc/vdd): 1.42 V ~ 1.58 V
• Data Converters: A/D 44x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 416-BGA
• Packages: PG-BGA-416
• Max Clock Frequency: 150.0 MHz
• Sram (incl. Cache): 256.0 KByte
• Can Nodes: 4
• A / D Input Lines (incl. Fadc): 44
• Program Memory: 2.0 MB
• For Use With: B158-H8537-G2-X-7600IN - KIT STARTER TC179X FAMILY
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: KT1796256F150EBDXP; SAK-TC1796-256F150EBDIN; SP000228336

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3.6
The Peripheral Control Processor (PCP2) in the TC1796 performs tasks that would
normally be performed by the combination of a DMA controller and its supporting CPU
interrupt service routines in a traditional computer system. It could easily be considered
as the host processor’s first line of defence as an interrupt-handling engine. The PCP2
can off-load the CPU from having to service time-critical interrupts. This provides many
benefits, including:
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The PCP2 has an architecture that efficiently supports DMA-type transactions to and
from arbitrary devices and memory addresses within the TC1796 and also has
reasonable stand-alone computational capabilities.
The PCP2 in the TC1796 contains an improved version of the TC1775’s PCP with the
following enhancements:
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The PCP2 is made up of several modular blocks as follows (see
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Data Sheet
Data buffering supported
– Code prefetch buffer
– Read/write buffer
External bus arbitration control capability for the EBU bus
Automatic self-configuration on boot from external memory
Avoiding large interrupt-driven task context-switching latencies in the host processor
Reducing the cost of interrupts in terms of processor register and memory overhead
Improving the responsiveness of interrupt service routines to data-capture and data-
transfer operations
Easing the implementation of multitasking operating systems.
Optimized context switching
Support for nested interrupts
Enhanced instruction set
Enhanced instruction execution speed
Enhanced interrupt queueing
PCP2 Processor Core
Code Memory (CMEM)
Parameter Memory (PRAM)
PCP2 Interrupt Control Unit (PICU)
PCP2 Service Request Nodes (PSRN)
System bus interface to the Flexible Peripheral Interface (FPI Bus)
Peripheral Control Processor
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Functional Description
Figure
5):
V1.0, 2008-04
TC1796