SAK-TC1796-256F150E BD Infineon Technologies, SAK-TC1796-256F150E BD Datasheet - Page 7

• Manufacturer Part Number: SAK-TC1796-256F150E BD
• Description: IC MCU 32BIT FLASH PG-BGA-416
• Manufacturer: Infineon Technologies
• Series: TC17xxr

Specifications of SAK-TC1796-256F150E BD

• Core Processor: TriCore
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: ASC, CAN, EBI/EMI, MLI, MSC, SSC
• Peripherals: DMA, POR, WDT
• Number Of I /o: 123
• Program Memory Size: 2MB (2M x 8)
• Program Memory Type: FLASH
• Ram Size: 256K x 8
• Voltage - Supply (vcc/vdd): 1.42 V ~ 1.58 V
• Data Converters: A/D 44x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 416-BGA
• Packages: PG-BGA-416
• Max Clock Frequency: 150.0 MHz
• Sram (incl. Cache): 256.0 KByte
• Can Nodes: 4
• A / D Input Lines (incl. Fadc): 44
• Program Memory: 2.0 MB
• For Use With: B158-H8537-G2-X-7600IN - KIT STARTER TC179X FAMILY
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: KT1796256F150EBDXP; SAK-TC1796-256F150EBDIN; SP000228336

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Data Sheet
High-performance 32-bit super-scalar TriCore V1.3 CPU with 4-stage pipeline
– Superior real-time performance
– Strong bit handling
– Fully integrated DSP capabilities
– Single precision Floating Point Unit (FPU)
– 150 MHz operation at full temperature range
32-bit Peripheral Control Processor with single cycle instruction (PCP2)
– 16 Kbyte Parameter Memory (PRAM)
– 32 Kbyte Code Memory (CMEM)
Multiple on-chip memories
– 2 Mbyte Program Flash Memory (PFLASH) with ECC
– 128 Kbyte Data Flash Memory (DFLASH) usable for EEPROM emulation
– 136 Kbyte Data Memory (LDRAM, SRAM, SBRAM)
– 8 Kbyte Dual-Ported Memory (DPRAM)
– 48 Kbyte Code Scratchpad Memory (SPRAM)
– 16 Kbyte Instruction Cache (ICACHE)
– 16 Kbyte BootROM (BROM)
16-Channel DMA Controller
32-bit External Bus Interface Unit (EBU) with
– 75 dedicated address/data bus, clock, and control lines
– Synchronous burst Flash access capability
Sophisticated interrupt system with 2 × 255 hardware priority arbitration levels
serviced by CPU or PCP2
High performing on-chip bus structure
– Two 64-bit Local Memory Buses between EBU, Flash and Data Memory
– 32-bit System Peripheral Bus (SPB) for on-chip peripheral and functional units
– 32-bit Remote Peripheral Bus (RPB) for high-speed on-chip peripheral units
– Two bus bridges (LFI Bridge, DMA Controller)
Peripheral Control Processor with single cycle instruction (PCP2)
– 16 Kbyte Parameter Memory (PRAM)
– 32 Kbyte Code Memory (CMEM)
Versatile On-chip Peripheral Units
– Two Asynchronous/Synchronous Serial Channels (ASC) with baud rate generator,
– Two High-Speed Synchronous Serial Channels (SSC) with programmable data
– Two serial Micro Second Bus interfaces (MSC) for serial port expansion to external
– Two High-Speed Micro Link interfaces (MLI) for serial inter-processor
parity, framing and overrun error detection
length and shift direction
power devices
communication
Summary of Features
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Summary of Features
V1.0, 2008-04
TC1796