SAK-TC1796-256F150E BD Infineon Technologies, SAK-TC1796-256F150E BD Datasheet - Page 104

• Manufacturer Part Number: SAK-TC1796-256F150E BD
• Description: IC MCU 32BIT FLASH PG-BGA-416
• Manufacturer: Infineon Technologies
• Series: TC17xxr

Specifications of SAK-TC1796-256F150E BD

• Core Processor: TriCore
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: ASC, CAN, EBI/EMI, MLI, MSC, SSC
• Peripherals: DMA, POR, WDT
• Number Of I /o: 123
• Program Memory Size: 2MB (2M x 8)
• Program Memory Type: FLASH
• Ram Size: 256K x 8
• Voltage - Supply (vcc/vdd): 1.42 V ~ 1.58 V
• Data Converters: A/D 44x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 416-BGA
• Packages: PG-BGA-416
• Max Clock Frequency: 150.0 MHz
• Sram (incl. Cache): 256.0 KByte
• Can Nodes: 4
• A / D Input Lines (incl. Fadc): 44
• Program Memory: 2.0 MB
• For Use With: B158-H8537-G2-X-7600IN - KIT STARTER TC179X FAMILY
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: KT1796256F150EBDXP; SAK-TC1796-256F150EBDIN; SP000228336

4.2.6
???
Table 21
Parameter
PORST low current at
V
PORST low current at
V
current without any port
activity
Active mode core
supply current
Active mode analog
supply current
Stand-by RAM supply
current in stand-by
Oscillator and PLL core
power supply
Oscillator and PLL pads
power supply
LVDS port supply
(via
Flash power supply
current
Maximum Allowed
Power Dissipation
1) Infineon Power Loop: CPU and PCP running, all peripherals active. The power consumption of each custom
2) The
3)
4) In case the LVDS pads are disabled, the power consumption pro pair is negligible (less than 1µA).
5) For the calculation of junction to ambient thermal resistance
Data Sheet
DD
DDP
application will most probably be lower than this value, but must be evaluated separately.
Infineon Max Power Loop.
The dependency in this range is, at constant junction temperature, linear.
V
in future steps and products is kept open.
DDOSC
V
, and PORST high
DDP
I
DD
and
)
decreases for typically 120 mA if the
4)
Power Supply Current
V
SSOSC
Power Supply Currents (Operating Conditions apply)
1)2)
are not bonded externally in the BC and BD steps of TC1796. An option for bonding them
5)
Symbol
I
I
I
I
I
I
I
I
I
I
P
DD_PORST
DDP_PORST
DD
DDAx;
DDMx
SBSB
DDOSC
DDOSC3
LVDS
DDFL3
D
3)
CC
CC
CC
CC
CC
CC
CC
CC
SR
CC
f
CPU
Min. Typ. Max.
–
–
10
–
–
–
–
–
–
–
104
is decreased for 50 MHz, at constant
Values
–
–
–
–
–
–
–
–
–
–
R
TJA
, see
300
25
700
–
9
5
3.6
50
80
P
R
<
25
D
TJA
o
×
C
Page
Unit Note /
mA
mA
mA
mA
mA
mA
mA
mA
mA
–
130.
Electrical Parameters
Test Condition
The PLL running at
the base frequency
The PLL running at
the base frequency
f
SYS
See ADC0/1
FADC
V
T
–
–
LVDS pads active
–
worst case
T
CPU
j
A
DDSB
= 150
= 125
= 2:1
=150MHz
T
= 1V,
J
V1.0, 2008-04
o
= 150C, for the
o
C
C
TC1796
f
CPU
/
f