SAK-TC1796-256F150E BD Infineon Technologies, SAK-TC1796-256F150E BD Datasheet

IC MCU 32BIT FLASH PG-BGA-416

SAK-TC1796-256F150E BD

Manufacturer Part Number
SAK-TC1796-256F150E BD
Description
IC MCU 32BIT FLASH PG-BGA-416
Manufacturer
Infineon Technologies
Series
TC17xxr
Datasheet

Specifications of SAK-TC1796-256F150E BD

Core Processor
TriCore
Core Size
32-Bit
Speed
150MHz
Connectivity
ASC, CAN, EBI/EMI, MLI, MSC, SSC
Peripherals
DMA, POR, WDT
Number Of I /o
123
Program Memory Size
2MB (2M x 8)
Program Memory Type
FLASH
Ram Size
256K x 8
Voltage - Supply (vcc/vdd)
1.42 V ~ 1.58 V
Data Converters
A/D 44x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
416-BGA
Packages
PG-BGA-416
Max Clock Frequency
150.0 MHz
Sram (incl. Cache)
256.0 KByte
Can Nodes
4
A / D Input Lines (incl. Fadc)
44
Program Memory
2.0 MB
For Use With
B158-H8537-G2-X-7600IN - KIT STARTER TC179X FAMILY
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
KT1796256F150EBDXP
SAK-TC1796-256F150EBDIN
SP000228336
D a ta S he e t , V 1 .0 , Ap r . 2 0 0 8
TC1796
3 2 - B i t S i n g l e - C h i p M i c ro c o n t r o ll e r
T r i C o r e
M i c r o c o n t r o l l e rs

Related parts for SAK-TC1796-256F150E BD

SAK-TC1796-256F150E BD Summary of contents

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TC1796 ...

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... Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life ...

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TC1796 ...

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... Green package variant included. 133 Example of a temperature profile corrected. Trademarks TriCore® trademark of Infineon Technologies AG. We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. ...

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Table of Contents 1 Summary of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Pad Driver and Pad Classes Summary . . . . . . . . . . . . . . . . . . . . . . . . . 83 4.1.3 Absolute Maximum Ratings . . . ...

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Summary of Features • High-performance 32-bit super-scalar TriCore V1.3 CPU with 4-stage pipeline – Superior real-time performance – Strong bit handling – Fully integrated DSP capabilities – Single precision Floating Point Unit (FPU) – 150 MHz operation at full ...

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One MultiCAN Module with four CAN nodes and 128 free assignable message objects for high efficiency data handling via FIFO buffering and gateway data transfer (one CAN node supports TTCAN functionality) – Two General Purpose Timer Array Modules (GPTA) ...

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... For the available ordering codes for the TC1796 please refer to the “Product Catalog Microcontrollers”, which summarizes all available microcontroller variants. This document describes the derivatives of the device.The derivatives and summarizes the differences. Table 1 TC1796 Derivative Synopsis Derivative SAK-TC1796-256F150E Data Sheet Summary of Features Table 1 Ambient Temperature Range o o ...

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General Device Information 2.1 TC1796 Block Diagram PMI 48 KB SPRAM 16 KB ICACHE Program Local Memory Bus PBCU P LMB PMU 16 KB BROM 2 MB PFLASH EBU 128 KB DFLASH Emulation Memory Interface OCDS Debug Interface /JTAG ...

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Logic Symbol TSTRES TESTMODE HDRST General Control PORST NMI BYPASS XTAL1 XTAL2 V Oscillator D D OSC V D DOSC3 V SSOSC TRST TCK TDI TDO JTAG / TMS OCDS BRKIN BRKOUT TR[15:0] TRCLK V D DEBU V D ...

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Pin Configuration N.C. P2.9 P2.13 P2.15 P0.14 P0.5 P0.2 B P2.6 P2.7 P2.10 P2.14 P0.9 P0.6 P0.4 C P2.5 P2.8 P2.11 P2.12 P0.12 P0.10 P0 P2.4 P2.3 P2.2 P0.15 ...

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Pad Driver and Input Classes Overview The TC1796 provides different types and classes of input and output lines. For understanding of the abbreviations in overview on the pad type and class types. 2.5 Pin Definitions and Functions Data Sheet ...

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Table 2 Pin Definitions and Functions Symbol Pins I/O Pad Class External Bus Interface Lines (EBU) D[31:0] I T26 I/O D1 T24 I/O D2 U26 I/O D3 T25 I/O D4 V26 I/O D5 U25 I/O D6 U23 I/O ...

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Table 2 Pin Definitions and Functions (cont’d) Symbol Pins I/O Pad Class A[23: J24 O A1 J25 O A2 J26 O A3 K25 O A4 K26 O A5 J23 O A6 K24 O A7 L25 O A8 ...

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Table 2 Pin Definitions and Functions (cont’d) Symbol Pins I/O Pad Class BFCLKO AF25 O B2 BFCLKI AF24 AF20 O B1 RD/WR AF21 O B1 ADV AF22 O B1 MR/W AF19 BC0 AE17 O ...

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Table 2 Pin Definitions and Functions (cont’d) Symbol Pins I/O Pad Class Parallel Ports P0 I/O A1 P0.0 A9 I/O P0.1 A8 I/O P0.2 A7 I/O P0.3 B8 I/O P0.4 B7 I/O P0.5 A6 I/O P0.6 B6 I/O P0.7 C8 ...

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Table 2 Pin Definitions and Functions (cont’d) Symbol Pins I/O Pad Class P1 I/O A1/ ...

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Table 2 Pin Definitions and Functions (cont’d) Symbol Pins I/O Pad Class P2 I/O A1/ P2.8 ...

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Table 2 Pin Definitions and Functions (cont’d) Symbol Pins I/O Pad Class P3 I/O A1 P3.0 B12 P3.1 A12 P3.2 C13 P3.3 B11 P3.4 C12 P3.5 A11 P3.6 B10 P3.7 C9 P3.9 D10 P3.8 C11 P3.10 C10 P3.11 D13 P3.12 ...

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Table 2 Pin Definitions and Functions (cont’d) Symbol Pins I/O Pad Class P4 I/O A1/A2 P4.0 AD10 I/O A2 P4.1 AE10 I/O A2 P4.2 AD11 I/O A2 P4.3 AE11 I/O A2 P4.4 AC12 I/O A2 P4.5 AD12 I/O A2 P4.6 ...

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Table 2 Pin Definitions and Functions (cont’d) Symbol Pins I/O Pad Class P5 I/O A2 P5.0 B13 I/O P5.1 A13 O P5.2 A14 I/O P5.3 B14 O P5.4 C15 O O P5.5 C14 I P5.6 B15 O O P5.7 A15 ...

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Table 2 Pin Definitions and Functions (cont’d) Symbol Pins I/O Pad Class P6 I P6.6 E3 I I/O P6 P6. ...

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Table 2 Pin Definitions and Functions (cont’d) Symbol Pins I/O Pad Class P7 I ...

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Table 2 Pin Definitions and Functions (cont’d) Symbol Pins I/O Pad Class P8 I/O A1/A2 P8 I I I I/O A2 P8.4 ...

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Table 2 Pin Definitions and Functions (cont’d) Symbol Pins I/O Pad Class P9 I/O A2 P9.0 A19 I/O O P9.1 B19 I/O O P9.2 B20 I/O O P9.3 A20 I/O O P9.4 D18 I/O O P9.5 D19 I/O O P9.6 ...

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Table 2 Pin Definitions and Functions (cont’d) Symbol Pins I/O Pad Class P10 I A1 P10.0 A21 I P10.1 B21 I P10.2 C21 I P10.3 D21 I Dedicated Peripheral I/Os SLSO0 AE14 O A2 SLSO1 AC15 O MTSR0 AF15 O ...

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Table 2 Pin Definitions and Functions (cont’d) Symbol Pins I/O Pad Class MSC Outputs C FCLP0A C18 O FCLN0 C17 O SOP0A C16 O SON0 D17 O FCLP1A A17 O FCLN1 B17 O SOP1A B16 O SON1 A16 O Data ...

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Table 2 Pin Definitions and Functions (cont’d) Symbol Pins I/O Pad Class Analog Inputs AN[43: AN0 AE1 I AN1 AD2 I AN2 AA4 I AN3 AB3 I AN4 AC2 I AN5 AA3 I AN6 AD1 I AN7 AB4 ...

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Table 2 Pin Definitions and Functions (cont’d) Symbol Pins I/O Pad Class D AN32 AC3 I AN33 AE2 I AN34 AD3 I AN35 AD5 I AN36 AE3 I AN37 AF2 I AN38 AC4 I AN39 AF3 I AN40 AD4 I ...

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Table 2 Pin Definitions and Functions (cont’d) Symbol Pins I/O Pad Class System I/O TRST F23 I A2 TCK E24 I A2 TDI E25 I A1 TDO D25 O A2 TMS F24 I A1 BRKIN C26 I/O A3 BRK D26 ...

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Table 2 Pin Definitions and Functions (cont’d) Symbol Pins I/O Pad Class XTAL1 G26 I n.a. XTAL2 G25 O N.C. A1 – – C22 G23 H3 AF1 AF26 AC21 AD23 AE22 AE23 Power Supplies V W4 – – DDM V ...

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Table 2 Pin Definitions and Functions (cont’d) Symbol Pins I/O Pad Class V H23 – – DDEBU H24 H25 H26 M23 T23 Y23 AC18 AC22 V B26 – – DD C25 D9 D16 D24 E23 H4 P23 R4 V23 AB23 ...

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In case of a power-fail condition (one or more power supply voltages drop below the specified voltage range), an undefined output driving level may occur at these pins. 3) Not bonded externally in the BC and BD steps of ...

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Pull-Up/Pull-Down Behavior of the Pins Table 4 List of Pull-Up/Pull-Down Reset Behavior of the Pins Pins PORST = 0 TSTRES, Weak pull-up device active TDI, TMS, TESTMODE, BRKOUT, BRKIN, all GPIOs, RD, RD/WR, ADV, BC[3:0], MR/W, WAIT, BAA, HOLD, ...

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Functional Description The following section gives an overview of the sub systems and the modules of the TC1796 and their connectivity. 3.1 System Architecture and On-Chip Bus Systems The TC1796 has four independent on-chip buses (see also TC1796 block ...

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On-Chip Memories As shown in the TC1796 block diagram on on-chip memories that are used as program or data memory. • Program memory in PMU and PMI – 2 Mbyte on-chip Program Flash (PFLASH) – 16 Kbyte Boot ROM ...

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JEDEC standard based command sequences for PFLASH control – Write state machine controls programming and erase operations – Status and error reporting by status flags and interrupt • Margin check for detection of problematic PFLASH bits Features of the ...

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Architectural Address Map Table 5 shows the overall architectural address map as defined for the TriCore and implemented in TC1796. Table 5 TC1796 Architectural Address Map Seg- Contents Size ment 8 × 256 0-7 Global Mbyte 8 Global 256 ...

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Memory Protection System The TC1796 memory protection system specifies the addressable range and read/write permissions of memory segments available to the currently executing task. The memory protection system controls the position and range of addressable segments in memory. It ...

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External Bus Unit The External Bus Unit (EBU) of the TC1796 is the units that controls the transactions between external memories or peripheral units with the internal memories and peripheral units. The EBU is a part of the PMU ...

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Data buffering supported – Code prefetch buffer – Read/write buffer • External bus arbitration control capability for the EBU bus • Automatic self-configuration on boot from external memory 3.6 Peripheral Control Processor The Peripheral Control Processor (PCP2) in the ...

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Code Memory CMEM FPI-Interface FPI Bus Figure 5 PCP2 Block Diagram Table 6 PCP2 Instruction Set Overview Instruction Group Description DMA primitives Efficient DMA channel implementation Load/Store Transfer data between PRAM or FPI memory and the general purpose registers, as ...

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DMA Controller and Memory Checker The Direct Memory Access (DMA) Controller of the TC1796 transfers data from data source locations to data destination locations without intervention of the CPU or other on-chip devices. One data move operation is controlled ...

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Features • 16 independent DMA channels – 8 DMA channels in each DMA Sub-Block – selectable request inputs per DMA channel – 2-level programmable priority of DMA channels within a DMA Sub-Block – Software and hardware DMA ...

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Note: Although the polynomial above is used for generation, the generation algorithm differs from the one that is used by the Ethernet protocol. 3.8 Interrupt System The TC1796 interrupt system provides a flexible and time-efficient means for processing interrupts. An ...

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Service Requestors 2 MSC0 2 MSC1 4 MLI0 2 MLI1 3 SSC0 3 SSC1 4 ASC0 4 ASC1 16 MultiCAN 4 ADC0 4 ADC1 4 FADC 38 GPTA0 38 GPTA1 16 LTCA2 2 STM 1 FPU 1 Flash 2 Ext. ...

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Asynchronous/Synchronous Serial Interfaces (ASC0, ASC1) Figure 8 shows a global view of the functional blocks and interfaces of the two Asynchronous/Synchronous Serial Interfaces ASC0 and ASC1. f Clock ASC Control Address Decoder EIR TBIR Interrupt TIR Control RIR ASC0_RDR ...

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Mode, 8-bit or 9-bit data transfer, parity generation, and the number of stop bits can be selected. Parity, framing, and overrun error detection are provided to increase the reliability of data transfers. Transmission and reception of data are double-buffered. For ...

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High-Speed Synchronous Serial Interfaces (SSC0, SSC1) Figure 9 shows a global view of the functional blocks and interfaces of the two High- Speed Synchronous Serial interfaces SSC0 and SSC1. f SSC0 Clock f Control CLC0 Address Decoder EIR TIR ...

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Mode). Data width, shift direction, clock polarity and phase are programmable. This allows communication with SPI- compatible devices. Transmission and reception of data is double-buffered. A shift clock generator provides the ...

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Micro Second Bus Interfaces (MSC0, MSC1) The Micro Second Channel (MSC) interfaces provides a serial communication link typically used to connect power switches or other peripheral devices. The serial communication link is build fast synchronous downstream ...

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The downstream and upstream channels of the MSC module communicate with the external world via nine I/O lines. Eight output lines are required for the serial communication of the downstream channel (clock, data, and enable signals). One out of eight ...

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MultiCAN Controller (CAN) Figure 11 shows a global view of the MultiCAN module with its functional blocks and interfaces. f CAN Clock f Control CLC Address Decoder Message Object Buffer DMA 128 Objects INT_O [3:0] Interrupt Control INT_O [15:4] ...

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CAN node, and it transmits only messages belonging to this message object list. A powerful, command-driven list controller performs all message object list operations. MultiCAN Features • CAN functionality ...

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Time-Triggered Extension (TTCAN) In addition to the event-driven CAN functionality, a deterministic behavior can be achieved for CAN node extension module that supports time-triggered CAN (TTCAN) functionality. The TTCAN protocol is compliant with the confirmed standardization proposal ...

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Micro Link Serial Bus Interface (MLI0, MLI1) The Micro Link Interface (MLI fast synchronous serial interface that allows to exchange data between microcontrollers of the 32-bit AUDO microcontroller family without intervention of a CPU or other bus ...

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MLI0 Clock f Control DMA Address Decoder MLI0 Module SR[3:0] Interrupt (Kernel) Control SR[7:4] To DMA BRKOUT Cerberus f MLI1 Clock f Control DMA Address Decoder MLI1 Module SR[1:0] Interrupt (Kernel) Control SR[3:2] Not Connected SR[7:4] To DMA BRKOUT ...

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General Purpose Timer Array The GPTA provides a set of timer, compare and capture functionalities that can be flexibly combined to form signal measurement and signal generation units. They are optimized for tasks typical of engine, gearbox, and electrical ...

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Functionality of GPTA0/GPTA1 Each of the General Purpose Timer Arrays (GPTA0 and GPTA1) provides a set of hardware modules required for high speed digital signal processing: • Filter and Prescaler Cells (FPC) support input noise filtering and prescaler operation. ...

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Mode, GPTA signal frequency in 3-sensor Mode. • Duty Cycle Measurement (DCM) – Four independent units – 100% margin and time-out handling f – maximum resolution GPTA f – ...

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I/O Sharing Unit • Interconnecting inputs and outputs from internal clocks, FPC, GTC, LTC, ports, and MSC interface. 3.14.2 Functionality of LTCA2 One Local Timer Cells Area provides a set of Local Timer Cells. • 64 Local Timer Cells (LTCs) ...

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Analog-to-Digital Converter (ADC0, ADC1) The two ADC modules of the TC1796 are analog to digital converters with 8-bit, 10-bit, or 12-bit resolution including sample & hold functionality. V AGND0 f ADC Clock f Control CLC Address Decoder SR [3:0] ...

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The A/D converters operate by the method of the successive approximation. A multiplexer selects between analog inputs that can be connected with the 16 conversion channels in each ADC module. An automatic self-calibration adjusts the ADC modules ...

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Fast Analog-to-Digital Converter Unit (FADC) The FADC module of the TC1796 basically is a 4-channel A/D converter with 10-bit resolution that operates by the method of the successive approximation. The main FADC functional blocks shown in • The Input ...

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FADC Clock f Control CLC Address Decoder SR[3:0] Interrupt Control To DMA OUT1 OUT9 OUT18 OUT26 GPTA0 OUT2 OUT10 OUT19 OUT27 External Request Unit (SCU) Figure 16 Block Diagram of the FADC Module Features • Extreme fast conversion: 21 ...

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System Timer The TC1796’s STM is designed for global system timing applications requiring both high precision and long range. Features • Free-running 56-bit counter • All 56 bits can be read synchronously • Different 32-bit portions of the 56-bit ...

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Figure 17 shows an overview on the System Timer with the options for reading parts of STM contents. STMIR1 Interrupt Control STMIR0 Enable / Disable Clock f Control STM STM_TIM5 Address Decoder PORST Figure 17 General Block Diagram of the ...

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Watchdog Timer The Watchdog Timer (WDT) provides a highly reliable and secure way to detect and recover from software or hardware failure. The WDT helps to abort an accidental malfunction of the TC1796 in a user-specified time period. When ...

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Important debugging support is provided through the reset pre-warning operation by first issuing an NMI to the CPU before finally resetting the device after a certain period of time. 3.19 System Control Unit The System Control Unit (SCU) of ...

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Table 7 TC1796 Boot Selections BRKIN HWCFG Type of Boot [3:0] Normal Boot Options 1 0000 Enter bootstrap loader mode 1: B Serial ASC0 boot via ASC0 pins 0001 Enter bootstrap loader mode 2: B Serial CAN boot via CAN ...

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Table 7 TC1796 Boot Selections (cont’d) BRKIN HWCFG Type of Boot [3:0] Debug Boot Options 0 0000 Tri-state chip B 1000 Go to external emulator space with EBU as B master, using CSEMU/CSCOMB Others Reserved; execute stop loop; 1) The ...

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Power Management System The TC1796 power management system allows software to configure the various processing units so that they automatically adjust to draw the minimum necessary power for the application. There are three power management modes: • Run Mode ...

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On-Chip Debug Support Figure 18 shows a block diagram of the TC1796 OCDS system. M TR[15: TRCLK TDI TDO JTAG TMS Controller TCK TRST BRKIN BRKOUT Figure 18 OCDS System Block Diagram The TC1796 basically supports three ...

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OCDS Level 1 Debug Support The OCDS Level 1 debug support is mainly assigned for real-time software debugging purposes which have a demand for low-cost standard debugger hardware. The OCDS Level 1 debug support is based on a JTAG interface ...

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Clock Generation and PLL The TC1796 clock system performs the following functions: • Acquires and buffers incoming clock signals to create a master clock frequency • Distributes in-phase synchronized clock signals throughout the TC1796’s entire clock tree • Divides ...

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VCO equal to or CPU CPU XTAL1 Main f OSC Osc. Circuit XTAL2 Osc. Run Detect. BYPASS Oscillator Control Register OSC_CON P5.3 / TXD1A Figure 19 Clock Generation Unit Recommended Oscillator Circuits The ...

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Oscillation measurement with the final target system is strongly recommended to verify the input amplitude at XTAL1 and to determine the actual oscillation allowance (margin negative resistance) for the ...

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Please refer to the minimum and maximum values of the negative resistance specified by the crystal supplier. 3.24 Power Supply The TC1796 has several power supply lines for different voltage classes: • 1.5 V: Core logic ...

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Identification Register Values The Identification Registers uniquely identify a module or the whole device. Table 9 TC1796 Identification Registers Short Name Address SCU_ID F000 0008 MANID F000 0070 CHIPID F000 0074 RTID F000 0078 SBCU_ID F000 0108 STM_ID F000 ...

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Table 9 TC1796 Identification Registers (cont’d) Short Name Address ADC0_ID F010 0408 MLI0_ID F010 C008 MLI1_ID F010 C108 MCHK_ID F010 C208 CPS_ID F7E0 FF08 CPU_ID F7E1 FE18 EBU_ID F800 0008 PMU_ID F800 0508 FLASH_ID F800 2008 DMU_ID F801 0108 DBCU_ID ...

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Electrical Parameters 4.1 General Parameters 4.1.1 Parameter Interpretation The parameters listed in this section partly represent the characteristics of the TC1796 and partly its requirements on the system. To aid interpreting the parameters easily when evaluating them for a ...

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Pad Driver and Pad Classes Summary This section gives an overview on the different pad driver classes and its basic characteristics. More details (mainly DC parameters) are defined in the Table 10 Pad Driver and Pad Classes Overview Class ...

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Absolute Maximum Ratings Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated ...

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Operating Conditions The following operating conditions must not be exceeded in order to ensure correct operation of the TC1796. All parameters specified in the following table refer to these operating conditions, unless otherwise noticed. The following operating conditions must ...

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Table 12 Operating Condition Parameters Parameter Absolute sum of short circuit currents of the device External load capacitance 1) Digital supply voltages applied to the TC1796 must be static regulated voltages which allow a typical voltage swing of ±5%. V ...

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Table 13 Pin Groups for Overload/Short-Circuit Current Sum Parameter Group Pins 9 D[7:0] 10 A[23:16] 11 A[15:8] 12 A[7:0] 13 TSTRES, TDI, TMS, TCK, TRST, TDO, BRKOUT, BRKIN, TESTMODE 14 P10.[3:0], BYPASS, NMI, PORST, HDRST 15 P9.[8:0] 16 FCLP[1:0]A, FCLN[1:0], ...

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DC Parameters 4.2.1 Input/Output Pins Table 14 Input/Output DC-Characteristics (Operating Conditions apply) Parameter Symbol General Parameters 1) I Pull-up current | | PUH I Pull-down | | PDL 1) current 1) C Pin capacitance IO (Digital I/O) V Input ...

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Table 14 Input/Output DC-Characteristics (cont’d)(Operating Conditions apply) Parameter Symbol V Class A Pads ( = 3. 3.3V ± 5%) DDP V Output low OLA 4) voltage V Output high OHA 3) voltage V Input low voltage ...

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Table 14 Input/Output DC-Characteristics (cont’d)(Operating Conditions apply) Parameter Symbol V Class B Pads ( = 2.375 to 3.47 V) DDEBU V Output low voltage OLB V Output high OHB voltage V Input low voltage ILB V Input high voltage IHB ...

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Function verified by design, value verified by design characterization. Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It cannot be guaranteed that it suppresses switching due to external system noise. = 2.5 V ...

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Analog to Digital Converters (ADC0/ADC1) Table 15 ADC Characteristics (Operating Conditions apply) Parameter Symbol V Analog supply DDM voltage Analog ground SSM voltage V Analog reference AREFx 17) voltage V Analog reference AGNDx 17) ground V ...

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Table 15 ADC Characteristics (cont’d) (Operating Conditions apply) Parameter Symbol 11)5) Gain error TUE GAIN 11)5) Offset error TUE OFF I Input leakage OZ1 current at analog inputs AN0, AN1, AN4 to AN7, AN24 to AN31. see Figure 24 13) ...

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Table 15 ADC Characteristics (cont’d) (Operating Conditions apply) Parameter Symbol R Resistance of the AREF reference voltage 16) input path C Total capacitance AINTOT of the analog 16) inputs C Switched AINSW capacitance at the analog voltage inputs R ON ...

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ADC module capability. 9) Not subject to production test, verified by design / characterization. 10) Value under typical application conditions due to integration (switching noise, etc.). 11) The sum of DNL/INL/Gain/Offset errors does not exceed the related TUE total ...

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Table 16 Sample and Conversion Time (Operating Conditions apply) Parameter Symbol Min. t Sample CC S time 8 × t Conversion CC C time A/D Converter Module Fractional f CLC Divider Arbiter (1:20) Figure 22 ADC0/ADC1 Clock Circuit Data Sheet ...

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R EXT AIN EXT V AREF Figure 23 ADC0/ADC1 Input Circuits Data Sheet Analog Input Circuitry R ANx AIN AINTOT V R AGNDx AIN7T Reference Voltage Input Circuitry R V AREF, On AREFx C - ...

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3uA 1uA 400nA 300nA -200nA 2% -1uA I OZ1 3uA 1uA 300nA 200nA -200nA 2% -1uA Figure 24 ADC0/ADC1Analog Inputs Leakage Data Sheet AN0, AN1, AN4 - AN7, AN24 - AN31 95% Others 95% 98% 98 TC1796 ...

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Fast Analog to Digital Converter (FADC) Table 17 FADC Characteristics (Operating Conditions apply) Parameter Symbol E DNL error DNL E INL error INL 1)10) E Gradient error GRAD E GRAD E GRAD 10) E Offset error OFF E Reference ...

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Table 17 FADC Characteristics (Operating Conditions apply) (cont’d) Parameter Symbol t Conversion time C f Converter Clock ADC R Input resistance of FAIN the analog voltage path (Rn, Rp) f Channel Amplifier COFF Cutoff Frequency t Settling Time of a ...

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FAINxN V FAGN D FAINxP V V FAR EF V Figure 25 FADC Input Circuits Data Sheet FADC Analog Input Stage FAR FADC Reference Voltage Input Circuitry FAR EF I FAR EF FAGN D ...

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Oscillator Pins Table 18 Oscillator Pins Characteristics (Operating Conditions apply) Parameter Symbol f Frequency Range OSC V Input low voltage at ILX 1) XTAL1 V Input high voltage at IHX 1) XTAL1 I Input current at IX1 XTAL1 1) ...

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Temperature Sensor Table 19 Temperature Sensor Characteristics (Operating Conditions apply) Parameter Symbol T Temperature SR Sensor Range t Start-up time after TSST resets inactive T Sensor Inaccuracy TSA f A/D Converter clock ANA for DTS signal Table 20 Temperature ...

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Power Supply Current ??? Table 21 Power Supply Currents (Operating Conditions apply) Parameter PORST low current PORST low current and PORST high DDP current without any port activity Active mode core 1)2) supply ...

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AC Parameters All AC parameters are defined with the temperature compensation disabled. That means, keeping the pads constantly at maximum strength. 4.3.1 Testing Waveforms V DDP V DDEBU 10 Figure 26 Rise/Fall Time Parameters V DDP V ...

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Output Rise/Fall Times Table 22 Output Rise/Fall Times (Operating Conditions apply) Parameter Symbol Class A1 Pads t t Rise/fall , RA1 FA1 1) times Class A2 Pads t t Rise/fall , RA2 FA2 1) times Class A3 Pads t ...

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Parameter test correlation for 4.3.3 Power Sequencing There is a restriction for the power sequencing of the 3.3 V domain including shown in Figure 29: it must always be higher than 1.5 V domain - 0.5 V. The grey ...

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V V DDP DDEBU, V DDFL3 V DDPmin V PORST3 DDmin V PORST1.5min Figure 30 Power Down / Power Loss Sequence Data Sheet Power Supply Voltage 3.3V 3.13V PORST 1.5V 1.42V PORST PowerDown3.3_1.5_reset_only.vsd 108 TC1796 Electrical ...

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Power, Pad and Reset Timing Table 23 Power, Pad and Reset Timing Parameters Parameter V Min. voltage to ensure DDP 1) defined pad states 2) Oscillator start-up time Minimum PORST active time after power supplies are stable at operating ...

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This parameter is valid under assumption that PORST signal is constantly at low level during the power- V up/power-down of the . DDP defined from the moment when OSCS 0, This parameter is verified ...

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V DDPPA V DDP oscs OSC t POA t POA PORST HDRST 2) Pads Pad- state undefined Figure 31 Power, Pad and Reset Timing Data Sheet programmed 2) Tri-state, pull ...

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Phase Locked Loop (PLL) Note: All PLL characteristics defined on this and the next page are verified by design characterization. Table 24 PLL Parameters (Operating Conditions apply) Parameter Accumulated jitter VCO frequency range 1) PLL base frequency PLL lock-in ...

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Note: The frequency of system clock P With rising number of clock cycles the maximum jitter increases linearly value P of that is defined by the K-factor of the PLL. Beyond this value of accumulated jitter remains ...

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D P ±3.5 ±3.0 ±2.5 ±2.0 ±1.5 ±1.0 ±0.5 ±0 Max. jitter Number of consecutive K-divider of PLL Figure 33 Approximated Maximum Accumulated PLL Jitter for Typical CPU ...

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BFCLKO Output Clock Timing 1.5 V ± 5 -40 °C to +125 ° Table 25 BFCLK0 Output Clock Timing Parameters Parameter BFCLKO clock period BFCLKO high time ...

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BFCLK Timing and PLL Jitter The BFCLK timing is important for calculating the timing of an external flash memory. In principle BFCLK timing can be derived from the PLL jitter formulas. In case of only EBU synchronous read access to ...

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Debug Trace Timing 3.13 to 3.47 V (Class A); SS DDP C C (TRCLK pF; (TR[15:0 pF Table 26 Debug Trace Timing Parameter Parameter TR[15:0] new state ...

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JTAG Interface Timing Operating Conditions apply Table 27 TCK Clock Timing Parameter Parameter 1) TCK clock period TCK high time TCK low time TCK clock rise time TCK clock fall time f 1) should be ...

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Table 28 JTAG Timing Parameters Parameter TMS setup to TCK rising edge TMS hold to TCK rising edge TDI setup to TCK rising edge TDI hold to TCK rising edge TDO valid output from TCK 2) falling edge TDO high ...

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EBU Demultiplexed Timing 1.5 V ± 5 -40 °C to +125 ° Table 29 EBU Demultiplexed Timing Parameters Parameter Output delay from BFCLKO 2) rising edge RD ...

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Demultiplexed Read Timing Address Phase BFCLKO t 10 A[23: ADV t 10 CS[3:0] CSCOMB RD RD/WR MR/W D[31: BC[3:0] WAIT Figure 38 EBU Demultiplexed Read Timing Data Sheet Command Del. Command Phase (opt.) Phase Valid ...

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Demultiplexed Write Timing Address Phase BFCLKO t 10 A[23: ADV t 10 CS[3:0] CSCOMB RD RD/ MR/W D[31: BC[3: WAIT Figure 39 EBU Demultiplexed Write Timing Data Sheet Command Del. Command ...

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EBU Burst Mode Read Timing 1.5 V ± 5 -40 °C to +125 ° Table 30 EBU Burst Mode Read Timing Parameters Parameter Output delay from BFCLKO ...

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Address Phase(s) BFCLKI 1) BFCLKO t 10 A[23: ADV t 10 CS[3:0] CSCOMB RD BAA D[31:0] (32-Bit) D[15:0] (16-Bit WAIT Output delays are always referenced to BCLKO. The reference clock for input 1) characteristics depends on ...

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EBU Arbitration Signal Timing 1.5 V ± 5 -40°C to +125 ° Table 31 EBU Arbitration Signal Timing Parameters Parameter Output delay from CLKOUT rising edge Data ...

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Peripheral Timings Note: Peripheral timing parameters are not subject to production test. They are verified by design/characterization. 4.3.12.1 Micro Link Interface (MLI) Timing Table 32 MLI Timing Parameters (Operating Conditions apply), C Parameter 1)2) TCLK clock period RCLK clock ...

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TCLKx TDATAx TVALIDx TREADYx RCLKx RDATAx RVALIDx RREADYx Figure 42 MLI Interface Timing Note: The generation of RREADYx is in the input clock domain of the receiver. The reception of TREADYx is asynchronous to TCLKx. Data Sheet ...

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Micro Second Channel (MSC) Interface Timing Table 33 MSC Interface Timing (Operating Conditions apply), C Parameter 1)2) FCLP clock period SOP/ENx outputs delay from FCLP rising edge SDI bit time SDI rise time SDI fall time 1) FCLP signal ...

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Synchronous Serial Channel (SSC) Master Mode Timing Table 34 SSC Master Mode Timing (Operating Conditions apply), C Parameter 1)2) SCLK clock period MTSR/SLSOx delay from SCLK rising edge MRST setup to SCLK falling edge MRST hold from SCLK falling ...

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Package and Reliability 5.1 Package Parameters (P/PG-BGA-416-4) Table 35 Thermal Characteristics of the Package Parameter Thermal resistance junction 1) case top Thermal resistance junction 1) case bottom 1) The top and bottom thermal resistances between the case and the ...

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Package Outline A26 Figure 45 P/PG-BGA-416-4, Plastic Low Profile Pitch Ball Grid Array You can find our packages, sorts of packing and others in our Infineon Internet Web Site. Data Sheet 416x +0.07 ...

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Flash Memory Parameters The data retention time of the TC1796’s Flash memory (i.e. the time after which stored data can still be retrieved) depends on the number of times the Flash memory has been erased and programmed. Table 36 ...

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Quality Declarations Table 37 Quality Parameters Parameter Symbol t Operation OP 1)2) Lifetime V ESD susceptibility HBM according to Human Body Model (HBM) V ESD susceptibility HBM1 of the LVDS pins V ESD susceptibility CDM according to Charged Device ...

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... Published by Infineon Technologies AG ...

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