HD64F2676VFC33 Renesas Electronics America, HD64F2676VFC33 Datasheet - Page 427

• Manufacturer Part Number: HD64F2676VFC33
• Description: IC H8S MCU FLASH 256K 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2676VFC33

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: IrDA, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 103
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Figure 8.21 Example of Block Transfer Mode Transfer Activated by EDREQ
EDREQ pin sampling is performed in each cycle starting at the next rise of after the end of the
EDMDR write cycle for setting the transfer-enabled state.
When a low level is sampled at the EDREQ pin while acceptance via the EDREQ pin is possible,
the request is held within the EXDMAC. Then when activation is initiated within the EXDMAC,
the request is cleared. At the end of the write cycle, acceptance resumes and EDREQ pin low level
sampling is performed again; this sequence of operations is repeated until the end of the transfer.
[1]
[2], [5] Request is cleared at end of next bus cycle, and activation is started in EXDMAC.
[3], [6] DMA cycle is started.
[4], [7] Acceptance is resumed after completion of dead cycle.
EDREQ
Address bus
DMA control
Channel
Acceptance after transfer enabling; EDREQ pin low level is sampled at rise of , and request is held.
(As in [1], EDREQ pin low level is sampled at rise of , and request is held.)
Idle
[1]
Minimum 3 cycles
Request
Bus release
[2]
Read
Request clearance period
[3]
Transfer source
DMA read
One block transfer
Write
DMA write
destination
Transfer
Idle
Acceptance
resumed
[4]
Minimum 3 cycles
Request
Bus release
Rev. 3.00 Mar 17, 2006 page 375 of 926
[5]
Read
Request clearance period
[6]
Transfer source
DMA read
Section 8 EXDMA Controller
One block transfer
Write
EDREQ Pin Low Level
EDREQ
EDREQ
DMA write
destination
Transfer
REJ09B0283-0300
Idle
Acceptance
resumed
[7]
Bus release