HD64F2676VFC33 Renesas Electronics America, HD64F2676VFC33 Datasheet - Page 347

• Manufacturer Part Number: HD64F2676VFC33
• Description: IC H8S MCU FLASH 256K 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2676VFC33

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: IrDA, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 103
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

7.5.4
Repeat mode can be specified by setting the RPE bit in DMACR to 1, and clearing the DTIE bit in
DMABCRL to 0. In repeat mode, MAR is updated after each byte or word transfer in response to
a single transfer request, and this is executed the number of times specified in ETCRL. On
completion of the specified number of transfers, MAR and ETCRL are automatically restored to
their original settings and operation continues. One address is specified by MAR, and the other by
IOAR. The transfer direction can be specified by the DTDIR bit in DMACR. Table 7.7
summarizes register functions in repeat mode.
Table 7.7
MAR specifies the start address of the transfer source or transfer destination as 24 bits. MAR is
incremented or decremented by 1 or 2 each time a byte or word is transferred. IOAR specifies the
lower 16 bits of the other address. The upper 8 bits of IOAR have a value of H'FF. The number of
transfers is specified as 8 bits by ETCRH and ETCRL. The maximum number of transfers, when
H'00 is set in both ETCRH and ETCRL, is 256.
Register
23
23
H'FF
15
Repeat Mode
7
7
MAR
ETCRH
ETCRL
Register Functions in Repeat Mode
IOAR
0
0
0
0
DTDIR = 0
Source
address
register
Destination
address
register
Holds number of
transfers
Transfer counter
Function
DTDIR = 1 Initial Setting
Destination
address
register
Source
address
register
Rev. 3.00 Mar 17, 2006 page 295 of 926
Start address of
transfer destination
or transfer source
Start address of
transfer source or
transfer destination
Number of transfers
Number of transfers
Section 7 DMA Controller (DMAC)
REJ09B0283-0300
Operation
Incremented/
decremented
every transfer.
Initial setting is
restored when
value reaches
H'0000
Fixed
Fixed
Decremented
every transfer.
Loaded with
ETCRH value
when count
reaches H'00