HD64F2676VFC33 Renesas Electronics America, HD64F2676VFC33 Datasheet - Page 294

• Manufacturer Part Number: HD64F2676VFC33
• Description: IC H8S MCU FLASH 256K 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2676VFC33

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: IrDA, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 103
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 6 Bus Controller (BSC)
DRAM space read
External write
DRAM space read
T
T
T
T
T
T
T
T
T
T
p
r
c1
c2
i
1
2
3
c1
c2
Address bus
RD
HWR, LWR
RAS
UCAS, LCAS
Data bus
Idle cycle
Figure 6.77 Example of Idle Cycle Operation after DRAM Access
(Write after Read) (IDLC = 0, RAST = 0, CAST = 0)
Normal space access after DRAM space write access
While the ICIS2 bit is set to 1 in BCR (there is no ICRS2 bit in the H8S/2678 Group, therefore
this setting cannot be made) and a normal space read access occurs after DRAM space write
access, idle cycle is inserted in the first read cycle. The number of states of the idle cycle to be
inserted is in accordance with the setting of the IDLC bit. It does not depend on the DRMI bit in
DRACCR. Figure 6.78 shows an example of idle cycle operation when the ICIS2 bit is set to 1.
Rev. 3.00 Mar 17, 2006 page 242 of 926
REJ09B0283-0300