HD64F2676VFC33 Renesas Electronics America, HD64F2676VFC33 Datasheet - Page 184

• Manufacturer Part Number: HD64F2676VFC33
• Description: IC H8S MCU FLASH 256K 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2676VFC33

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: IrDA, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 103
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 6 Bus Controller (BSC)
6.3.4
RDNCR selects the read strobe signal (RD) negation timing in a basic bus interface read access.
Bit
7
6
5
4
3
2
1
0
Rev. 3.00 Mar 17, 2006 page 132 of 926
REJ09B0283-0300
RDNn = 0
RDNn = 1
Bit Name
RDN7
RDN6
RDN5
RDN4
RDN3
RDN2
RDN1
RDN0
Figure 6.2 Read Strobe Negation Timing (Example of 3-State Access Space)
Read Strobe Timing Control Register (RDNCR)
RD
Data
RD
Data
Initial Value
0
0
0
0
0
0
0
0
T
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
Description
Read Strobe Timing Control 7 to 0
These bits set the negation timing of the read
strobe in a corresponding area read access.
As shown in figure 6.2, the read strobe for an
area for which the RDNn bit is set to 1 is negated
one half-state earlier than that for an area for
which the RDNn bit is cleared to 0. The read data
setup and hold time specifications are also one
half-state earlier.
0: In an area n read access, the RD is negated at
1: In an area n read access, the RD is negated
the end of the read cycle
one half-state before the end of the read cycle
Bus cycle
T
2
T
3
(n = 7 to 0)