HD64F2676VFC33 Renesas Electronics America, HD64F2676VFC33 Datasheet - Page 336

• Manufacturer Part Number: HD64F2676VFC33
• Description: IC H8S MCU FLASH 256K 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2676VFC33

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: IrDA, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 103
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 7 DMA Controller (DMAC)
chain transfer. When re-setting the control register area, perform masking by setting bits in
DMAWER to prevent modification of the contents of other channels.
Writes by the DTC to bits 15 to 12 (FAE and SAE) in DMABCR are invalid regardless of the
DMAWER settings. These bits should be changed, if necessary, by CPU processing.
In writes by the DTC to bits 7 to 4 (DTE) in DMABCR, 1 can be written without first reading 0.
To reactivate a channel set to full address mode, write 1 to both Write Enable A and Write Enable
B for the channel to be reactivated.
MAR, IOAR, and ETCR can always be written to regardless of the DMAWER settings. When
modifying these registers, the channel to be modified should be halted.
Rev. 3.00 Mar 17, 2006 page 284 of 926
REJ09B0283-0300
Figure 7.2 Areas for Register Re-Setting by DTC (Channel 0A)
DTC
Second transfer area
using chain transfer
First transfer area
DMACR_0A
DMACR_1A
DMAWER
ETCR_0A
ETCR_0B
ETCR_1A
ETCR_1B
IOAR_0A
IOAR_0B
IOAR_1A
IOAR_1B
MAR_0A
MAR_0B
MAR_1A
MAR_1B
DMABCR
DMACR_0B
DMACR_1B
DMATCR