HD64F2676VFC33 Renesas Electronics America, HD64F2676VFC33 Datasheet - Page 178

• Manufacturer Part Number: HD64F2676VFC33
• Description: IC H8S MCU FLASH 256K 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2676VFC33

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: IrDA, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 103
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 6 Bus Controller (BSC)
6.3.1
ABWCR designates each area in the external address space as either 8-bit access space or 16-bit
access space.
Bit
7
6
5
4
3
2
1
0
Note:
6.3.2
ASTCR designates each area in the external address space as either 2-state access space or 3-state
access space.
Bit
7
6
5
4
3
2
1
0
Rev. 3.00 Mar 17, 2006 page 126 of 926
REJ09B0283-0300
* In modes 2, 4, and 6, ABWCR is initialized to 1. In modes 1, 5, and 7, ABWCR is
Bit Name
ABW7
ABW6
ABW5
ABW4
ABW3
ABW2
ABW1
ABW0
Bit Name
AST7
AST6
AST5
AST4
AST3
AST2
AST1
AST0
Bus Width Control Register (ABWCR)
Access State Control Register (ASTCR)
initialized to 0.
Initial Value *
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
Initial Value
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Area 7 to 0 Bus Width Control
These bits select whether the corresponding
area is to be designated as 8-bit access space
or 16-bit access space.
0: Area n is designated as 16-bit access space
1: Area n is designated as 8-bit access space
Description
Area 7 to 0 Access State Control
These bits select whether the corresponding
area is to be designated as 2-state access
space or 3-state access space. Wait state
insertion is enabled or disabled at the same
time.
0: Area n is designated as 2-state access space
1: Area n is designated as 3-state access space
Wait state insertion in area n access is
disabled
Wait state insertion in area n access is
enabled
(n = 7 to 0)
(n = 7 to 0)