HD64F2676VFC33 Renesas Electronics America, HD64F2676VFC33 Datasheet - Page 306

• Manufacturer Part Number: HD64F2676VFC33
• Description: IC H8S MCU FLASH 256K 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2676VFC33

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: IrDA, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 103
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 6 Bus Controller (BSC)
Rev. 3.00 Mar 17, 2006 page 254 of 926
REJ09B0283-0300
Figure 6.85 Bus Release State Transition Timing when Synchronous DRAM Interface
DQMU, DQML
Precharge-sel
Address bus
SDRAM
Data bus
[1] Low level of BREQ signal is sampled at rise of f.
[2] PLL command is issued.
[3] Bus control signal returns to be high at end of external space access cycle.
[4] BACK signal is driven low, releasing bus to external bus master..
[5] BREQ signal state is also sampled in external bus released state.
[6] High level of BREQ signal is sampled.
[7] BACK signal is driven high, ending external bus release cycle.
[8] When there is external access or refresh request of internal bus master during
[9] BREQO signal goes high 1.5 states after rising edge of BACK signal. If BREQO
BREQO
BREQ
BACK
At least one state from sampling of BREQ signal.
external bus release while the BREQOE bit is set to 1, BREQO signal goes low.
signal is asserted because of auto-refreshing request, it retains low until auto-refresh cycle starts up.
RAS
CAS
CKE
WE
External space read
NOP
T
1
[1]
T
2
[2]
PALL
[3]
address
NOP
Row
[4]
External bus released state
[5]
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
[8]
[6]
[7]
NOP
[9]
CPU
cycle