HD64F2676VFC33 Renesas Electronics America, HD64F2676VFC33 Datasheet - Page 345

• Manufacturer Part Number: HD64F2676VFC33
• Description: IC H8S MCU FLASH 256K 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2676VFC33

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: IrDA, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 103
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

by IOAR. The transfer direction can be specified by the DTDIR bit in DMACR. Table 7.6
summarizes register functions in idle mode.
Table 7.6
MAR specifies the start address of the transfer source or transfer destination as 24 bits. MAR is
neither incremented nor decremented by a data transfer. IOAR specifies the lower 16 bits of the
other address. The upper 8 bits of IOAR have a value of H'FF.
Figure 7.5 illustrates operation in idle mode.
The number of transfers is specified as 16 bits in ETCR. ETCR is decremented by 1 each time a
transfer is executed, and when its value reaches H'0000, the DTE bit is cleared and data transfer
ends. If the DTIE bit is set to 1 at this time, an interrupt request is sent to the CPU or DTC. The
maximum number of transfers, when H'0000 is set in ETCR, is 65,536.
Transfer requests (activation sources) consist of external requests, SCI transmission complete and
reception complete interrupts, and TPU channel 0 to 5 compare match/input capture A interrupts.
Register
23
23
H'FF
15
MAR
15
MAR
Register Functions in Idle Mode
ETCR
IOAR
0
0
0
Figure 7.5 Operation in Idle Mode
DTDIR = 0
Source
address
register
Destination
address
register
Transfer counter
Function
Transfer
1 byte or word transfer performed in
response to 1 transfer request
DTDIR = 1
Destination
address
register
Source
address
register
Rev. 3.00 Mar 17, 2006 page 293 of 926
Initial Setting
Start address of
transfer destination
or transfer source
Start address of
transfer source or
transfer destination
Number of transfers
Section 7 DMA Controller (DMAC)
REJ09B0283-0300
Operation
Fixed
Fixed
Decremented
every transfer;
transfer ends
when count
reaches H'0000
IOAR