HD64F2676VFC33 Renesas Electronics America, HD64F2676VFC33 Datasheet - Page 342

IC H8S MCU FLASH 256K 144-QFP

HD64F2676VFC33

Manufacturer Part Number
HD64F2676VFC33
Description
IC H8S MCU FLASH 256K 144-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2600r
Datasheets

Specifications of HD64F2676VFC33

Core Processor
H8S/2600
Core Size
16-Bit
Speed
33MHz
Connectivity
IrDA, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
103
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 4x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

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Section 7 DMA Controller (DMAC)
7.5.2
Sequential mode can be specified by clearing the RPE bit in DMACR to 0. In sequential mode,
MAR is updated after each byte or word transfer in response to a single transfer request, and this is
executed the number of times specified in ETCR. One address is specified by MAR, and the other
by IOAR. The transfer direction can be specified by the DTDIR bit in DMACR.
Table 7.5 summarizes register functions in sequential mode.
Table 7.5
Register
23
23
MAR specifies the start address of the transfer source or transfer destination as 24 bits. MAR is
incremented or decremented by 1 or 2 each time a byte or word is transferred. IOAR specifies the
lower 16 bits of the other address. The 8 bits above IOAR have a value of H'FF.
Figure 7.3 illustrates operation in sequential mode.
Rev. 3.00 Mar 17, 2006 page 290 of 926
REJ09B0283-0300
H'FF
15
15
Sequential Mode
MAR
Register Functions in Sequential Mode
ETCR
IOAR
0
0
0
DTDIR = 0
Source
address
register
Destination
address
register
Transfer counter
Function
DTDIR = 1
Destination
address
register
Source
address
register
Initial Setting
Start address of
transfer destination
or transfer source
Start address of
transfer source or
transfer destination
Number of transfers
Operation
Incremented/
decremented
every transfer
Fixed
Decremented
every transfer;
transfer ends
when count
reaches H'0000

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