HD64F2676VFC33 Renesas Electronics America, HD64F2676VFC33 Datasheet - Page 424

• Manufacturer Part Number: HD64F2676VFC33
• Description: IC H8S MCU FLASH 256K 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2676VFC33

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: IrDA, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 103
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 8 EXDMA Controller
EDREQ
EDREQ
EDREQ
EDREQ Pin Falling Edge Activation Timing: Figure 8.18 shows an example of normal mode
transfer activated by the EDREQ pin falling edge.
EDREQ pin sampling is performed in each cycle starting at the next rise of after the end of the
EDMDR write cycle for setting the transfer-enabled state.
When a low level is sampled at the EDREQ pin while acceptance via the EDREQ pin is possible,
the request is held within the EXDMAC. Then when activation is initiated within the EXDMAC,
the request is cleared, and EDREQ pin high level sampling for edge sensing is started. If EDREQ
pin high level sampling is completed by the end of the DMA write cycle, acceptance resumes after
the end of the write cycle, and EDREQ pin low level sampling is performed again; this sequence
of operations is repeated until the end of the transfer.
Figure 8.19 shows an example of block transfer mode transfer activated by the EDREQ pin falling
edge.
Rev. 3.00 Mar 17, 2006 page 372 of 926
REJ09B0283-0300
[1]
[2], [5] Request is cleared at end of next bus cycle, and activation is started in EXDMAC.
[3], [6] DMA cycle start; EDREQ pin high level sampling is started at rise of .
[4], [7] When EDREQ pin high level has been sampled, acceptance is resumed after completion of write cycle.
EDREQ
Address bus
DMA control
Channel
Figure 8.18 Example of Normal Mode Transfer Activated by EDREQ
Acceptance after transfer enabling; EDREQ pin low level is sampled at rise of , and request is held.
(As in [1], EDREQ pin low level is sampled at rise of ø, and request is held.)
Idle
[1]
Minimum 3 cycles
Request
Bus release
[2]
Read
[3]
Request clearance period
Transfer source
DMA read
Write
DMA write
destination
Transfer
Idle
Acceptance
resumed
[4]
Minimum 3 cycles
Request
Bus release
[5]
Read
[6]
Request clearance period
Transfer source
DMA read
EDREQ
EDREQ Pin Falling Edge
EDREQ
Write
DMA write Bus release
destination
Transfer
Idle
Acceptance
resumed
[7]