HD64F2676VFC33 Renesas Electronics America, HD64F2676VFC33 Datasheet - Page 11

• Manufacturer Part Number: HD64F2676VFC33
• Description: IC H8S MCU FLASH 256K 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2676VFC33

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: IrDA, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 103
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Item
10.15.4 Pin
Functions
10.16.4 Pin
Functions
11.1 Features
Table 11.1 TPU
Functions
11.3.9 Timer
Synchronous Register
(TSYR)
15.3.9 Bit Rate
Generator (BRR)
Table 15.2
Relationships
between N Setting in
BRR and Bit Rate B
Page
515
515
520
523
558
679
Revision (See Manual for Details)
• PG3/CS3/RAS3/CAS, PG2/CS2/RAS2/RAS
Description amended
The pin function is switched as shown below according to the
operating mode, bit EXPE, bit PGnDDR, bit CSnE, and bits
RMTS2 to RMTS0.
• PG1/CS1, PG0/CS0
Description amended
The pin function is switched as shown below according to the
operating mode, bit EXPE, bit PGnDDR, and bit CSnE.
• PH1/CS5/RAS5/SDRAM
Description amended
The pin function is switched as shown below according to the
operating mode, DCTL pin, bit EXPE, bit CS5E, bits RMTS2
to RMTS0, and bit PH1DDR.
Table 11.1 amended
Bits 7, 6 initial value amended
Table 15.2 amended
Item
DTC
activation
DMAC
activation
A/D
converter
trigger
PPG
trigger
Smart Card
Interface Mode
Mode
(Before) -
Channel 0
TGR
compare
match or
input capture
TGRA_0
compare
match or
input capture
TGRA_0
compare
match or
input capture
TGRA_0/
TGRB_0
compare
match or
input capture
Bit Rate
B =
(After) All 0
S
TGR
compare
match or
input capture
TGRA_1
compare
match or
input capture
TGRA_1
compare
match or
input capture
TGRA_1/
TGRB_1
compare
match or
input capture
Channel 1
2
2n 1
10
(N + 1)
6
Channel 2
TGR
compare
match or
input capture
TGRA_2
compare
match or
input capture
TGRA_2
compare
match or
input capture
TGRA_2/
TGRB_2
compare
match or
input capture
Rev. 3.00 Mar 17, 2006 page ix of l
Error
Error (%) =
Channel 3
TGR
compare
match or
input capture
TGRA_3
compare
match or
input capture
TGRA_3
compare
match or
input capture
TGRA_3/
TGRB_3
compare
match or
input capture
{
B
S
2
Channel 4
TGR
compare
match or
input capture
TGRA_4
compare
match or
input capture
TGRA_4
compare
match or
input capture
—
2n 1
10
6
(N + 1)
Channel 5
TGR
compare
match or
input capture
TGRA_5
compare
match or
input capture
TGRA_5
compare
match or
input capture
—
– 1
}
100