HD64F2676VFC33 Renesas Electronics America, HD64F2676VFC33 Datasheet - Page 360

• Manufacturer Part Number: HD64F2676VFC33
• Description: IC H8S MCU FLASH 256K 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2676VFC33

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: IrDA, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 103
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 7 DMA Controller (DMAC)
Transfer requests (activation sources) consist of external requests, SCI transmission complete and
reception complete interrupts, and TPU channel 0 to 5 compare match/input capture A interrupts.
Figure 7.16 shows an example of the setting procedure for block transfer mode.
Rev. 3.00 Mar 17, 2006 page 308 of 926
REJ09B0283-0300
and transfer destination
Set number of transfers
Block transfer mode
Set transfer source
Read DMABCRL
Set DMABCRH
Set DMABCRL
Block transfer
mode setting
Set DMACR
addresses
Figure 7.16 Example of Block Transfer Mode Setting Procedure
[1]
[2]
[3]
[4]
[5]
[6]
[1] Set each bit in DMABCRH.
[2] Set the transfer source address in MARA, and
[3] Set the block size in both ETCRAH and
[4] Set each bit in DMACRA and DMACRB.
[5] Read DTE = 0 and DTME = 0 in DMABCRL.
[6] Set each bit in DMABCRL.
• Set the FAE bit to 1 to select full address
• Specify enabling or disabling of internal
the transfer destination address in MARB.
ETCRAL. Set the number of transfers in
ETCRB.
• Set the transfer data size with the DTSZ bit.
• Specify whether MARA is to be incremented,
• Set the BLKE bit to 1 to select block transfer
• Specify whether the transfer source or the
• Specify whether MARB is to be incremented,
• Select the activation source with bits DTF3 to
• Specify enabling or disabling of transfer end
• Set both the DTME bit and the DTE bit to 1 to
mode.
interrupt clearing with the DTA bit.
decremented, or fixed, with the SAID and
SAIDE bits.
mode.
transfer destination is a block area with the
BLKDIR bit.
decremented, or fixed, with the DAID and
DAIDE bits.
DTF0.
interrupts to the CPU with the DTIE bit.
enable transfer.