HD64F2676VFC33 Renesas Electronics America, HD64F2676VFC33 Datasheet - Page 17

• Manufacturer Part Number: HD64F2676VFC33
• Description: IC H8S MCU FLASH 256K 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2676VFC33

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: IrDA, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 103
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 5 Interrupt Controller
5.1
5.2
5.3
5.4
5.5
5.6
5.7
Section 6 Bus Controller (BSC)
6.1
6.2
6.3
Features ............................................................................................................................. 85
Input/Output Pins .............................................................................................................. 87
Register Descriptions ........................................................................................................ 87
5.3.1
5.3.2
5.3.3
5.3.4
5.3.5
5.3.6
5.3.7
Interrupt Sources............................................................................................................... 101
5.4.1
5.4.2
Interrupt Exception Handling Vector Table...................................................................... 102
Interrupt Control Modes and Interrupt Operation ............................................................. 107
5.6.1
5.6.2
5.6.3
5.6.4
5.6.5
Usage Notes ...................................................................................................................... 117
5.7.1
5.7.2
5.7.3
5.7.4
5.7.5
5.7.6
Features ............................................................................................................................. 121
Input/Output Pins .............................................................................................................. 123
Register Descriptions ........................................................................................................ 125
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
6.3.6
Interrupt Control Register (INTCR)..................................................................... 88
Interrupt Priority Registers A to K (IPRA to IPRK) ............................................ 88
IRQ Enable Register (IER) .................................................................................. 91
IRQ Sense Control Registers H and L (ISCRH, ISCRL)..................................... 92
IRQ Status Register (ISR).................................................................................... 98
IRQ Pin Select Register (ITSR) ........................................................................... 98
Software Standby Release IRQ Enable Register (SSIER) ................................... 100
External Interrupts ............................................................................................... 101
Internal Interrupts................................................................................................. 102
Interrupt Control Mode 0 ..................................................................................... 108
Interrupt Control Mode 2 ..................................................................................... 110
Interrupt Exception Handling Sequence .............................................................. 112
Interrupt Response Times .................................................................................... 114
DTC and DMAC Activation by Interrupt ............................................................ 115
Contention between Interrupt Generation and Disabling..................................... 117
Instructions that Disable Interrupts ...................................................................... 118
Times when Interrupts are Disabled .................................................................... 118
Interrupts during Execution of EEPMOV Instruction.......................................... 119
Change of IRQ Pin Select Register (ITSR) Setting ............................................. 119
Note on IRQ Status Register (ISR) ...................................................................... 119
Bus Width Control Register (ABWCR)............................................................... 126
Access State Control Register (ASTCR) ............................................................. 126
Wait Control Registers AH, AL, BH, and BL
(WTCRAH, WTCRAL, WTCRBH, and WTCRBL)........................................... 127
Read Strobe Timing Control Register (RDNCR) ................................................ 132
CS Assertion Period Control Registers H, L (CSACRH, CSACRL)................... 133
Area 0 Burst ROM Interface Control Register (BROMCRH)
Area 1 Burst ROM Interface Control Register (BROMCRL).............................. 135
.......................................................................................... 85
...................................................................................... 121
Rev. 3.00 Mar 17, 2006 page xv of l