HD64F2676VFC33 Renesas Electronics America, HD64F2676VFC33 Datasheet - Page 369

• Manufacturer Part Number: HD64F2676VFC33
• Description: IC H8S MCU FLASH 256K 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2676VFC33

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: IrDA, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 103
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

DREQ pin sampling is performed every cycle, with the rising edge of the next cycle after the
end of the DMABCR write cycle for setting the transfer enabled state as the starting point.
When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is
possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the
request is cleared. After the end of the dead cycle, acceptance resumes, DREQ pin low level
sampling is performed again, and this operation is repeated until the transfer ends.
[1]
[2] [5] The request is cleared at the next bus break, and activation is started in the DMAC.
[3] [6] The DMA cycle is started.
[4] [7] Acceptance is resumed after the dead cycle is completed.
Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible.
DREQ
Address
bus
DMA
control
Channel
Figure 7.25 Example of DREQ
Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising edge of ,
and the request is held.
(As in [1], the DREQ pin low level is sampled on the rising edge of , and the request is held.)
Idle
Bus release
[1]
Request
of 2 cycles
Minimum
[2]
Read
[3]
Transfer source
Request clear period
DREQ Pin Low Level Activated Block Transfer Mode Transfer
DREQ
DREQ
DMA
read
Write
1 block transfer
Transfer destination
DMA
write
Acceptance resumes
Dead
[4]
Request
DMA
dead
of 2 cycles
Minimum
Idle
[5]
release
Bus
Rev. 3.00 Mar 17, 2006 page 317 of 926
Read
[6]
Transfer source
Section 7 DMA Controller (DMAC)
Request clear period
DMA
read
Write
1 block transfer
Transfer destination
DMA
write
Dead
REJ09B0283-0300
Acceptance resumes
DMA
dead
[7]
Idle
release
Bus