MCF5307AI90B Freescale Semiconductor, MCF5307AI90B Datasheet - Page 6

• Manufacturer Part Number: MCF5307AI90B
• Description: IC MPU 32BIT COLDF 90MHZ 208FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF530xr

Specifications of MCF5307AI90B

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 90MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, POR, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-FQFP
• Maximum Clock Frequency: 90 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 90MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: FQFP
• Program Memory Size: 8KB
• Cpu Speed: 90MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Paragraph
Number
2.1
2.1.1
2.1.2
2.1.2.1
2.1.2.1.1
2.1.2.2
2.1.2.2.1
2.1.2.2.2
2.1.2.2.3
2.1.3
2.2
2.2.1
2.2.1.1
2.2.1.2
2.2.1.3
2.2.1.4
2.2.1.5
2.2.2
2.2.2.1
2.2.2.2
2.2.2.3
2.2.2.4
2.2.2.5
2.2.2.6
2.3
2.4
2.4.1
2.4.2
2.5
2.6
2.6.1
2.7
2.7.1
2.7.2
2.7.3
2.7.4
vi
Features and Enhancements.............................................................................. 2-21
Programming Model ......................................................................................... 2-26
Integer Data Formats......................................................................................... 2-31
Organization of Data in Registers..................................................................... 2-31
Addressing Mode Summary ............................................................................. 2-33
Instruction Set Summary................................................................................... 2-34
Instruction Timing ............................................................................................ 2-40
Clock-Multiplied Microprocessor Core........................................................ 2-22
Enhanced Pipelines ....................................................................................... 2-22
Debug Module Enhancements ...................................................................... 2-25
User Programming Model ............................................................................ 2-27
Supervisor Programming Model................................................................... 2-29
Organization of Integer Data Formats in Registers ...................................... 2-31
Organization of Integer Data Formats in Memory ....................................... 2-32
Instruction Set Summary .............................................................................. 2-37
MOVE Instruction Execution Times ............................................................ 2-41
Execution Timings—One-Operand Instructions .......................................... 2-43
Execution Timings—Two-Operand Instructions.......................................... 2-43
Miscellaneous Instruction Execution Times................................................. 2-45
Instruction Fetch Pipeline (IFP)................................................................ 2-23
Operand Execution Pipeline (OEP) .......................................................... 2-24
Data Registers (D0–D7) ........................................................................... 2-27
Address Registers (A0–A6) ...................................................................... 2-27
Stack Pointer (A7, SP).............................................................................. 2-28
Program Counter (PC) .............................................................................. 2-28
Condition Code Register (CCR)............................................................... 2-28
Status Register (SR).................................................................................. 2-29
Vector Base Register (VBR) .................................................................... 2-30
Cache Control Register (CACR) .............................................................. 2-30
Access Control Registers (ACR0–ACR1)................................................ 2-31
RAM Base Address Register (RAMBAR) ............................................... 2-31
Module Base Address Register (MBAR) ................................................. 2-31
Branch Acceleration ............................................................................. 2-23
Illegal Opcode Handling....................................................................... 2-24
Hardware Multiply/Accumulate (MAC) Unit ...................................... 2-24
Hardware Divide Unit .......................................................................... 2-25
Freescale Semiconductor, Inc.
For More Information On This Product,
MCF5407 Processor Core
Go to: www.freescale.com
MCF5307 User’s Manual
CONTENTS
ColdFire Core
Chapter 2
Part I
Title
Number
Page