MCF5307AI90B Freescale Semiconductor, MCF5307AI90B Datasheet - Page 132

• Manufacturer Part Number: MCF5307AI90B
• Description: IC MPU 32BIT COLDF 90MHZ 208FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF530xr

Specifications of MCF5307AI90B

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 90MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, POR, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-FQFP
• Maximum Clock Frequency: 90 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 90MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: FQFP
• Program Memory Size: 8KB
• Cpu Speed: 90MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Real-Time Trace Support
0x8–
5.3.1 Begin Execution of Taken Branch (PST = 0x5)
PST is 0x5 when a taken branch is executed. For some opcodes, a branch target address may
be displayed on DDATA depending on the CSR settings. CSR also controls the number of
address bytes displayed, which is indicated by the PST marker value immediately
preceding the DDATA nibble that begins the data output.
Hex
0xB
0xC
0xD
0xE
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0xF
5-4
PST[3:0]
Binary
1000–
0000
0001
0010
0011
0100
0101
0110
0111
1011
1100
1101
1110
1111
Continue execution. Many instructions execute in one processor cycle. If an instruction requires more
clock cycles, subsequent clock cycles are indicated by driving PST outputs with this encoding.
Begin execution of one instruction. For most instructions, this encoding signals the first clock cycle of
an instruction’s execution. Certain change-of-flow opcodes, plus the PULSE and WDDATA instructions,
generate different encodings.
Reserved
Entry into user-mode. Signaled after execution of the instruction that caused the ColdFire processor to
enter user mode.
Begin execution of PULSE and WDDATA instructions. PULSE defines logic analyzer triggers for debug
and/or performance analysis. WDDATA lets the core write any operand (byte, word, or longword)
directly to the DDATA port, independent of debug module configuration. When WDDATA is executed, a
value of 0x4 is signaled on the PST port, followed by the appropriate marker, and then the data transfer
on the DDATA port. Transfer length depends on the WDDATA operand size.
Begin execution of taken branch. For some opcodes, a branch target address may be displayed on
DDATA depending on the CSR settings. CSR also controls the number of address bytes displayed,
indicated by the PST marker value preceding the DDATA nibble that begins the data output. See
Section 5.3.1, “Begin Execution of Taken Branch (PST = 0x5).”
Reserved
Begin execution of return from exception (RTE) instruction.
Indicates the number of bytes to be displayed on the DDATA port on subsequent clock cycles. The
value is driven onto the PST port one clock PSTCLK cycle before the data is displayed on DDATA.
0x8 Begin 1-byte transfer on DDATA.
0x9 Begin 2-byte transfer on DDATA.
0xA Begin 3-byte transfer on DDATA.
0xB Begin 4-byte transfer on DDATA.
Exception processing. Exceptions that enter emulation mode (debug interrupt or optionally trace)
generate a different encoding, as described below. Because the 0xC encoding defines a multiple-cycle
mode, PST outputs are driven with 0xC until exception processing completes.
Entry into emulator mode. Displayed during emulation mode (debug interrupt or optionally trace).
Because this encoding defines a multiple-cycle mode, PSToutputs are driven with 0xD until exception
processing completes.
Processor is stopped. Appears in multiple-cycle format when the MCF5307 executes a STOP
instruction. The ColdFire processor remains stopped until an interrupt occurs, thus PST outputs
display 0xE until the stopped mode is exited
Processor is halted. Because this encoding defines a multiple-cycle mode, the PST outputs display
0xF until the processor is restarted or reset. (see Section 5.5.1, “CPU Halt”)
Freescale Semiconductor, Inc.
Table 5-2. Processor Status Encoding
For More Information On This Product,
Go to: www.freescale.com
MCF5307 User’s Manual
.
Definition