MCF5307AI90B Freescale Semiconductor, MCF5307AI90B Datasheet - Page 143

• Manufacturer Part Number: MCF5307AI90B
• Description: IC MPU 32BIT COLDF 90MHZ 208FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF530xr

Specifications of MCF5307AI90B

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 90MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, POR, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-FQFP
• Maximum Clock Frequency: 90 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 90MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: FQFP
• Program Memory Size: 8KB
• Cpu Speed: 90MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

31–30
29/13
15:14
Bits
DRc[4–0]
A write to TDR clears the CSR trigger status bits, CSR[BSTAT].
Section Table 5-14., “TDR Field Descriptions,” describes how to handle multiple
breakpoint conditions.
Table 5-14 describes TDR fields.
Reset
Reset
Field
Field
R/W Write only. Accessible in supervisor mode as debug control register 0x07 using the WDEBUG instruction and
TRC
EBL
Name
LxT
through the BDM port using the
31
15
TRC
LxT
Trigger response control. Determines how the processor responds to a completed trigger condition. The
trigger response is always displayed on DDATA.
00 Display on DDATA only
01 Processor halt
10 Debug interrupt
11 Reserved
Level-x trigger. This is a Rev. B function. The Level-x Trigger bit determines the logic operation for the
trigger between the PC_condition and the (Address_range & Data_condition) where the inclusion of a
Data condition is optional. The ColdFire debug architecture supports the creation of single or double-level
triggers.
TDR[15]
0 Level-2 trigger = PC_condition & Address_range & Data_condition
1 Level-2 trigger = PC_condition | (Address_range & Data_condition)
TDR[14]
0 Level-1 trigger = PC_condition & Address_range & Data_condition
1 Level-1 trigger = PC_condition | (Address_range & Data_condition)
Enable breakpoint. Global enable for the breakpoint trigger. Setting TDR[EBL] enables a breakpoint
trigger. Clearing it disables all breakpoints.
30
14
The debug module has no hardware interlocks, so to prevent
spurious breakpoint triggers while the breakpoint registers are
being loaded, disable TDR (by clearing TDR[29,13] before
defining triggers.
EBL
EBL
29
13
Figure 5-12. Trigger Definition Register (TDR)
EDLW EDWL EDWU EDLL EDLM EDUM EDUU
EDLW EDWL EDWU EDLL EDLM EDUM EDUU
28
12
Freescale Semiconductor, Inc.
For More Information On This Product,
Table 5-14. TDR Field Descriptions
27
11
WDMREG
Chapter 5. Debug Support
Go to: www.freescale.com
26
10
command.
0000_0000_0000_0000
0000_0000_0000_0000
25
9
NOTE:
Second-Level Trigger
24
First-Level Trigger
8
Description
0x07
23
7
22
6
DI
DI
21
5
EAI EAR EAL EPC PCI
EAI EAR EAL EPC PCI
20
4
Programming Model
19
3
18
2
17
1
5-15
16
0