MCF5307AI90B Freescale Semiconductor, MCF5307AI90B Datasheet - Page 52

• Manufacturer Part Number: MCF5307AI90B
• Description: IC MPU 32BIT COLDF 90MHZ 208FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF530xr

Specifications of MCF5307AI90B

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 90MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, POR, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-FQFP
• Maximum Clock Frequency: 90 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 90MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: FQFP
• Program Memory Size: 8KB
• Cpu Speed: 90MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Programming Model, Addressing Modes, and Instruction Set
The PLL module’s three modes of operation are described as follows.
1.4 Programming Model, Addressing Modes, and
The ColdFire programming model has two privilege levels—supervisor and user. The S bit
in the status register (SR) indicates the privilege level. The processor identifies a logical
address that differentiates between supervisor and user modes by accessing either the
supervisor or user address space.
1-12
• Reset mode—When RSTI is asserted, the PLL enters reset mode. At reset, the PLL
• Normal mode—In normal mode, the input frequency programmed at reset is
• Reduced-power mode—In reduced-power mode, the PCLK is disabled by executing
• User mode—When the processor is in user mode (SR[S] = 0), only a subset of
• Supervisor mode—This mode protects system resources from uncontrolled access
asserts RSTO from the MCF5307. The core:bus frequency ratio and other MCF5307
configuration information are sampled during reset.
clock-multiplied to provide the processor clock (PCLK).
a sequence that includes programming a control bit in the system configuration
register (SCR) and then executing the STOP instruction. Register contents are
retained in reduced-power mode, so the system can be reenabled quickly when an
unmasked interrupt or reset is detected.
registers can be accessed, and privileged instructions cannot be executed. Typically,
most application processing occurs in user mode. User mode is usually entered by
executing a return from exception instruction (RTE, assuming the value of SR[S]
saved on the stack is 0) or a MOVE, SR instruction (assuming SR[S] is 0).
by users. In supervisor mode, complete access is provided to all registers and the
entire ColdFire instruction set. Typically, system programmers use the supervisor
programming model to implement operating system functions and provide I/O
Instruction Set
DIVIDE[1:0]
FREQ[1:0]
CLKIN
RSTI
Freescale Semiconductor, Inc.
For More Information On This Product,
CLKIN X 4
PLL
Figure 1-3. PLL Module
Go to: www.freescale.com
MCF5307 User’s Manual
Divide
by 2
Divide by 2,
3, or 4
RSTO
PCLK
PSTCLK
BCLKO