MCF5307AI90B Freescale Semiconductor, MCF5307AI90B Datasheet - Page 394

• Manufacturer Part Number: MCF5307AI90B
• Description: IC MPU 32BIT COLDF 90MHZ 208FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF530xr

Specifications of MCF5307AI90B

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 90MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, POR, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-FQFP
• Maximum Clock Frequency: 90 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 90MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: FQFP
• Program Memory Size: 8KB
• Cpu Speed: 90MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Data Transfer Operation
Table 18-4 describes the states as they appear in subsequent timing diagrams. Note that the
TT[1:0], TM[2:0], and TIP functions are chosen in the PAR, as described in Section 15.1.1,
“Pin Assignment Register (PAR).”
18-6
S0
S1
S2
S3
S4
State
All
All
Fast termination
Read/write
(skipped for fast
termination)
Write
Read/write
(skipped for fast
termination)
Read
All
Read (including
fast termination)
Cycle
Figure 18-4. Data Transfer State Transition Diagram
High
Low
High
Low
High
BCLKO
Freescale Semiconductor, Inc.
Next Cycle
S5
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S4
The read or write cycle is initiated. On the rising edge of BCLKO, the MCF5307
places a valid address on the address bus, asserts TIP, and drives R/W high for
a read and low for a write, if these signals are not already in the appropriate
state. The MCF5307 asserts TT[1:0], TM[2:0], SIZ[1:0], and TS on the rising
edge of BCLKO.
AS asserts on the falling edge of BCLKO, indicating that the address and
attributes are stable. The appropriate CSx, BE/BWE, and OE signals assert on
the BCLKO falling edge.
TA must be asserted during S1. Data is made available by the external device
and is sampled on the rising edge of BCLKO with TA asserted.
TS is negated on the rising edge of BCLKO.
The data bus is driven out of high impedance as data is placed on the bus on
the rising edge of BCLKO.
The MCF5307 waits for TA assertion. If TA is not sampled as asserted before
the rising edge of BCLKO at the end of the first clock cycle, the MCF5307
inserts wait states (full clock cycles) until TA is sampled as asserted.
Data is made available by the external device on the falling edge of BCLKO and
is sampled on the rising edge of BCLKO with TA asserted.
The external device should negate TA.
The external device can stop driving data after the rising edge of BCLKO.
However, data could be driven up to S5.
Table 18-4. Bus Cycle States
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Termination
MCF5307 User’s Manual
Fast
S0
S3
Wait
States
Description
S1
S2
Basic
Read/Write