MCF5307AI90B Freescale Semiconductor, MCF5307AI90B Datasheet - Page 429

• Manufacturer Part Number: MCF5307AI90B
• Description: IC MPU 32BIT COLDF 90MHZ 208FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF530xr

Specifications of MCF5307AI90B

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 90MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, POR, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-FQFP
• Maximum Clock Frequency: 90 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 90MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: FQFP
• Program Memory Size: 8KB
• Cpu Speed: 90MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

19.4.1 JTAG Instruction Shift Register
The MCF5307 IEEE Standard 1149.1 implementation uses a 3-bit instruction-shift register
(IR) without parity. This register transfers its value to a parallel hold register and applies
one of six instructions on the falling edge of TCK when the TAP state machine is in
Update-IR state. To load instructions into the shift portion of the register, place the serial
data on TDI before each rising edge of TCK. The msb of the instruction shift register is the
bit closest to the TDI pin, and the lsb is the bit closest to TDO.
Table 19-2 describes customer-usable instructions.
Instruction
PRELOAD
SAMPLE/
EXTEST
IDCODE
HIGHZ
(SMP)
(EXT)
(IDC)
(HIZ)
Required
Optional
Required
Optional
Class
000 Selects the boundary-scan register. Forces all output pins and bidirectional pins
001 Selects the IDCODE register for connection as a shift path between TDI and TDO.
100 Provides two separate functions. It obtains a sample of the system data and control
101 Anticipates the need to backdrive outputs and protects inputs from random toggling
IR
Chapter 19. IEEE 1149.1 Test Access Port (JTAG)
Freescale Semiconductor, Inc.
configured as outputs to the preloaded fixed values (with the SAMPLE/PRELOAD
instruction) and held in the boundary-scan update registers. EXTEST can also
configure the direction of bidirectional pins and establish high-impedance states on
some pins. EXTEST becomes active on the falling edge of TCK in the Update-IR state
when the data held in the instruction-shift register is equivalent to octal 0.
Interrogates the MCF5307 for version number and other part identification. The
IDCODE register is implemented in accordance with IEEE Standard 1149.1 so the lsb
of the shift register stage is set to logic 1 on the rising edge of TCK following entry into
the capture-DR state. Therefore, the first bit shifted out after selecting the IDCODE
register is always a logic 1. The remaining 31-bits are also set to fixed values. See
Section 19.4.2, “IDCODE Register.”
IDCODE is the default value in the IR when a JTAG reset occurs by either asserting
TRST or holding TMS high while clocking TCK through at least five rising edges and
the falling edge after the fifth rising edge. A JTAG reset causes the TAP state machine
to enter test-logic-reset state (normal operation of the TAP state machine into the
test-logic-reset state also places the default value of octal 1 into the instruction
register). The shift register portion of the instruction register is loaded with the default
value of octal 1 in Capture-IR state and a TCK rising edge occurs.
signals at the MCF5307 input pins and before the boundary-scan cell at the output
pins. This sampling occurs on the rising edge of TCK in the capture-DR state when an
instruction encoding of octal 4 is in the instruction register. Sampled data is observed
by shifting it through the boundary-scan register to TDO by using shift-DR state. The
data capture and shift are transparent to system operation. The users must provide
external synchronization to achieve meaningful results because there is no internal
synchronization between TCK and CLK.
SAMPLE/PRELOAD also initializes the boundary-scan register update cells before
selecting EXTEST or CLAMP. This is done by ignoring data shifted out of TDO while
shifting in initialization data. The Update-DR state in conjunction with the falling edge
of TCK can then transfer this data to the update cells. This data is applied to external
outputs when an instruction listed above is applied.
during board testing. Selects the bypass register, forcing all output and bidirectional
pins into high-impedance.
HIGHZ goes active on the falling edge of TCK in the Update-IR state when instruction
shift register data held is equivalent to octal 5.
For More Information On This Product,
Table 19-2. JTAG Instructions
Go to: www.freescale.com
Description
JTAG Register Descriptions
19-5