MCF5307AI90B Freescale Semiconductor, MCF5307AI90B Datasheet - Page 137

• Manufacturer Part Number: MCF5307AI90B
• Description: IC MPU 32BIT COLDF 90MHZ 208FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF530xr

Specifications of MCF5307AI90B

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 90MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, POR, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-FQFP
• Maximum Clock Frequency: 90 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 90MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: FQFP
• Program Memory Size: 8KB
• Cpu Speed: 90MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Table 5-5 describes ABLR fields.
Table 5-6 describes ABHR fields.
5.4.3 BDM Address Attribute Register (BAAR)
The BAAR defines the address space for memory-referencing BDM commands. See
Figure 5-7. The reset value of 0x5 sets supervisor data as the default address space.
Table 5-7 describes BAAR fields
DRc[4–0]
DRc[4–0]
31–0 Address High address. Holds the 32-bit address marking the upper bound of the address breakpoint range.
Bits
31–0
Bits
Reset
Reset
Field
Field
R/W Write only. BAAR[R,SZ] are loaded directly from the BDM command; BAAR[TT,TM] can be programmed as
R/W Write only. ABHR is accessible in supervisor mode as debug control register 0x0C using the WDEBUG
Address Low address. Holds the 32-bit address marking the lower bound of the address breakpoint range.
Name
Name
debug control register 0x05 from the external development system. For compatibility with Rev. A, BAAR is
loaded each time AATR is written.
instruction and via the BDM port using the
ABLR is accessible in supervisor mode as debug control register 0x0D using the WDEBUG instruction and
via the BDM port using the
31
R
7
Figure 5-6. Address Breakpoint Registers (ABLR, ABHR)
Breakpoints for specific addresses are programmed into ABLR.
Figure 5-7. BDM Address Attribute Register (BAAR)
6
Freescale Semiconductor, Inc.
For More Information On This Product,
Table 5-6. ABHR Field Description
Table 5-5. ABLR Field Description
SZ
WDMREG
Chapter 5. Debug Support
.
5
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command.
0x0D (ABLR); 0x0C (ABHR)
RDMREG
4
0000_0101
Address
Description
Description
0x05
TT
and
—
WDMREG
3
commands.
2
Programming Model
TM
1
0
5-9
0