MCF5307AI90B Freescale Semiconductor, MCF5307AI90B Datasheet - Page 478

• Manufacturer Part Number: MCF5307AI90B
• Description: IC MPU 32BIT COLDF 90MHZ 208FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF530xr

Specifications of MCF5307AI90B

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 90MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, POR, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-FQFP
• Maximum Clock Frequency: 90 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 90MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: FQFP
• Program Memory Size: 8KB
• Cpu Speed: 90MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Index-20
MAC status, 1-14, 2-29
MASK, 2-29
MBAR, 6-4
MPARK, 6-11
output port command, 14-15
PADAT, 15-2
PADDR, 15-2
PAR, 6-10, 15-1
parallel port
PLL control, 7-3
PLLCR, 7-3
read control, 5-36
read debug module, 5-38
reset status, 6-5
RSR, 6-5
S bit, 1-12
SDRAM mode initialization, 11-38
SIM
software watchdog interrupt, 6-9
status, 2-29
SWIVR, 6-9
SWSR, 6-9
SYPCR, 6-8
system protection control, 6-8
TCR, 13-4
TER, 13-5
timer module
TMR, 13-3
trigger definition, 5-14
UACR, 14-12
UART modules, 14-2–14-16
UCR, 14-9
UCSR, 14-8
UDU/UDL, 14-14
UIP, 14-15
UIPCR, 14-12
UISR, 14-13
UIVR, 14-15
vector base, 2-30
write control, 5-37
write debug module, 5-39
boundary scan, 19-7
bypass, 19-10
descriptions, 19-4
IDCODE, 19-6
instruction shift, 19-5
data, 15-2
pin assignment, 6-10, 15-1
base address, 6-4
memory map, 6-3
capture, 13-4
event, 13-5
mode, 13-3
reference, 13-4
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MCF5307 User’s Manual
INDEX
RSTI timing, 7-5
S
SDRAM
Signal descriptions, 17-1
block diagram and major components, 11-2
controller registers, A-3
DACR initialization, 11-35
DCR initialization, 11-35
definitions, 11-2
DMR initialization, 11-37
example, 11-34
initialization code, 11-39
interface configuration, 11-35
mode register initialization, 11-38
overview, 11-1
address
bus
chip-select module, 17-15
clock, 17-13
clock and reset signals
data bus, 17-8
data/configuration pins, 17-13
debug
DMA controller module, 17-17
DRAM controller
I
2
C module
bus, 17-7
configuration, 17-14
strobe, 17-9
arbitration, 17-12
clock output, 17-13
data, 17-8
driven, 17-13
grant, 17-12
request, 17-12
divide control, 17-15
high impedance, 17-20
JTAG, 17-21
processor clock output, 17-20
test
address strobes, 17-16
overview, 17-16
synchronous
write, 17-17
general, 17-19
serial data and clock, 17-19
clock, 17-23
mode, 17-20
overview, 17-20
clock enable, 17-17
column address strobe, 17-17
edge select, 17-17
row address strobe, 17-17