MCF5307AI90B Freescale Semiconductor, MCF5307AI90B Datasheet - Page 106

• Manufacturer Part Number: MCF5307AI90B
• Description: IC MPU 32BIT COLDF 90MHZ 208FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF530xr

Specifications of MCF5307AI90B

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 90MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, POR, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-FQFP
• Maximum Clock Frequency: 90 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 90MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: FQFP
• Program Memory Size: 8KB
• Cpu Speed: 90MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Cache Organization
A set is a group of four lines (one from each level, or way), corresponding to the same index
into the cache array.
4.8.1 Cache Line States: Invalid, Valid-Unmodified, and
As shown in Table 4-3, a cache line can be invalid, valid-unmodified (often called
exclusive), or valid-modified.
A valid line can be explicitly invalidated by executing a CPUSHL instruction.
4-8
Set 0
Set 1
Set 126
Set 127
V
0
1
1
Where:
TAG—21-bit address tag
V—Valid bit for line
M—Modified bit for line
Valid-Modified
M
0
1
x
TAG
Invalid. Invalid lines are ignored during lookups.
Valid, unmodified. Cache line has valid data that matches system memory.
Valid, modified. Cache line contains most recent data, data at system memory location is stale.
Way 0
Figure 4-3. Cache Organization and Line Format
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Table 4-3. Valid and Modified Bit Settings
V M
Freescale Semiconductor, Inc.
For More Information On This Product,
Longword 0
Go to: www.freescale.com
MCF5307 User’s Manual
Way 1
Line
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Cache Line Format
Longword 1
Description
Way 2
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Longword 2
Longword 3
Way 3
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